TI中文支持网Part Number:TMS320C6678
尊敬的ti工程师，烦请解答我的疑惑，已困扰已久；
我使用得是pdk库中得ddr3 初始化流程，代码见下面; 我发现
DDR_RDWR_LVL_RMP_CTRL = 0x80000000; //enable full leveling
DDR_RDWR_LVL_CTRL = 0x80000000; //Trigger full leveling – This ignores read DQS leveling result and uses ratio forced value
来启动fulling leveling貌似并没有效果，现象为：
1、等待leveling comlpete之后，DDR3_CONFIG_23寄存器中得4个RATIO值并没有发生改变；训练得意义就是得到四组RATIO最优值吧？
2、启动 fulling leveling之后，不管延时与否，leveling都会马上完成，不会发生超时；
3、是否是因为我的dsp的ddr memory control硬件版本不支持leveling？那么什么版本是支持的？我看STK的例程里说1.0版本只支持force ratio ；
初始化代码流程：
void ddr3_setup_auto_lvl_1333()
{
//int i,TEMP,startlo, stoplo,starthi, stophi;
int TEMP;
KICK0 = KICK0_UNLOCK;
KICK1 = KICK1_UNLOCK;
/* Wait for PLL to lock = min 500 ref clock cycles.
With refclk = 100MHz, = 5000 ns = 5us */
sleep_timer(1000);
/***************** 3.2 DDR3 PLL Configuration ************/
/* Done before */
/**************** 3.0 Leveling Register Configuration ********************/
/* Using partial automatic leveling due to errata */
/**************** 3.3 Leveling register configuration ********************/
DDR3_CONFIG_REG_0 &= ~(0x007FE000); // clear ctrl_slave_ratio field
DDR3_CONFIG_REG_0 |= 0x00200000; // set ctrl_slave_ratio to 0x100
DDR3_CONFIG_REG_12 |= 0x08000000; // Set invert_clkout = 1
DDR3_CONFIG_REG_0 |= 0xF; // set dll_lock_diff to 15
//From 4.2.1 Executing Partial Automatic Leveling — Start
DDR3_CONFIG_REG_23 |= 0x00000200; //Set bit 9 = 1 to use forced ratio leveling for read DQS
//From 4.2.1 Executing Partial Automatic Leveling — End
//Values with invertclkout = 1
/**************** 3.3 Partial Automatic Leveling ********************/
/*DATA0_WRLVL_INIT_RATIO = 0x78;
DATA1_WRLVL_INIT_RATIO = 0x76;
DATA2_WRLVL_INIT_RATIO = 0x72;
DATA3_WRLVL_INIT_RATIO = 0x76;
DATA4_WRLVL_INIT_RATIO = 0x69;
DATA5_WRLVL_INIT_RATIO = 0x69;
DATA6_WRLVL_INIT_RATIO = 0x5B;
DATA7_WRLVL_INIT_RATIO = 0x60;
DATA8_WRLVL_INIT_RATIO = 0x00;
DATA0_GTLVL_INIT_RATIO = 0xAF;
DATA1_GTLVL_INIT_RATIO = 0xB1;
DATA2_GTLVL_INIT_RATIO = 0xA3;
DATA3_GTLVL_INIT_RATIO = 0xA0;
DATA4_GTLVL_INIT_RATIO = 0x9B;
DATA5_GTLVL_INIT_RATIO = 0x9B;
DATA6_GTLVL_INIT_RATIO = 0x98;
DATA7_GTLVL_INIT_RATIO = 0x92;
DATA8_GTLVL_INIT_RATIO = 0x00; */
//Do a PHY reset. Toggle DDR_PHY_CTRL_1 bit 15 0->1->0
DDR_DDRPHYC &= ~(0x00008000);
DDR_DDRPHYC |= (0x00008000);
DDR_DDRPHYC &= ~(0x00008000);
/***************** 3.4 Basic Controller and DRAM Configuration ************/
DDR_SDRFC = 0x0000c34; // enable configuration
/* DDR_SDTIM1 = 0x1113783C; */
TEMP = 0;
TEMP |= 0x8 << 25; // T_RP bit field 28:25
TEMP |= 0x8 << 21; // T_RCD bit field 24:21
TEMP |= 0x9 << 17; // T_WR bit field 20:17
TEMP |= 0x17 << 12; // T_RAS bit field 16:12
TEMP |= 0x20 << 6; // T_RC bit field 11:6
TEMP |= 0x7 << 3; // T_RRD bit field 5:3
TEMP |= 0x4; // T_WTR bit field 2:0
DDR_SDTIM1 = 0x0AAAE4E2; //TEMP;
/* DDR_SDTIM2 = 0x30717FE3; */
TEMP = 0;
TEMP |= 0x3 << 28; // T_XP bit field 30:28
TEMP |= 0x71 << 16; // T_XSNR bit field 24:16
TEMP |= 0x1ff << 6; // T_XSRD bit field 15:6
TEMP |= 0x4 << 3; // T_RTP bit field 5:3
TEMP |= 0x3; // T_CKE bit field 2:0
DDR_SDTIM2 = 0x206B7FDA;//TEMP;
/* DDR_SDTIM3 = 0x559F86AF; */
TEMP = 0;
TEMP |= 0x5 << 28; // T_PDLL_UL bit field 31:28 (fixed value)
TEMP |= 0x5 << 24; // T_CSTA bit field 27:24 (fixed value)
TEMP |= 0x4 << 21; // T_CKESR bit field 23:21
TEMP |= 0x3f << 15; // T_ZQCS bit field 20:15
TEMP |= 0x6a << 4; // T_RFC bit field 12:4
TEMP |= 0xf; // T_RAS_MAX bit field 3:0 (fixed value)
DDR_SDTIM3 = 0x557F867F; //TEMP;
DDR_DDRPHYC = 0x0010010F;
DDR_ZQCFG = 0x70073214;
DDR_PMCTL = 0x0;
DDR_SDRFC = 0x0000c34; // enable configuration
/* DDR_SDCFG = 0x63062A32; */
/* New value with DYN_ODT disabled and SDRAM_DRIVE = RZQ/7 //0x63222A32; // last config write DRAM init occurs */
TEMP = 0;
TEMP |= 0x3 << 29; // SDRAM_TYPE bit field 31:29 (fixed value)
TEMP |= 0x0 << 27; // IBANK_POS bit field 28:27
TEMP |= 0x3 << 24; // DDR_TERM bit field 26:24
TEMP |= 0x0 << 21; // DYN_ODT bit field 22:21
TEMP |= 0x1 << 18; // SDRAM_DRIVE bit field 19:18
TEMP |= 0x2 << 16; // CWL bit field 17:16
TEMP |= 0x0 << 14; // NM bit field 15:14
TEMP |= 0xA << 10; // CL bit field 13:10
TEMP |= 0x4 << 7; // ROWSIZE bit field 9:7
TEMP |= 0x3 << 4; // IBANK bit field 6:4
TEMP |= 0x0 << 3; // EBANK bit field 3:3
TEMP |= 0x2; // PAGESIZE bit field 2:0
DDR_SDCFG = 0x63072B33;//TEMP;
//Wait 600us for HW init to complete
sleep_timer(100000);
DDR_SDRFC = 0x0000c34; //0x00001450; //Refresh rate = (7.8*666MHz)
/**************** 4.2.1 Executing Partial Automatic Leveling ********************/
DDR_RDWR_LVL_RMP_CTRL = 0x80000000; //enable full leveling
DDR_RDWR_LVL_CTRL = 0x80000000; //Trigger full leveling – This ignores read DQS leveling result and uses ratio forced value
//(0x34) instead
//Wait for min 1048576 DDR clock cycles for leveling to complete = 1048576 * 1.5ns = 1572864ns = 1.57ms.
//Actual time = ~10-15 ms
sleep_timer(100000);
//GEL_TextOut("\nDDR3 initialization is complete.\n");
}
Nancy Wang：
您是否有按照实际硬件设计的情况修改表格，并获取相应的值，表格的instruction部分都有说明。
我找了一篇文章，可以参考看一下，
blog.csdn.net/…/52684967
,
jj jj：
Nancy Wang，您好，您可能没看懂我的问题，我重新在这里做了描述，还麻烦您再解答一下，或者帮我转发ti 英文论坛，这个问题是我目前排查ddr不稳定唯一的线索，关于leveling在我的办卡上是否有效的执行了：
e2echina.ti.com/…/tms320c6678-ddr3-full-automatic-leveling-traning
,
Allen35065：
您要是最近采购的芯片都是2.0，1.0是2010年以前才可能会有的芯片。
DDR3 Leveling 的问题参考https://www.ti2k.com/wp-content/uploads/ti2k/DeyiSupport_DSP_sprz334h.pdf Errata Advisory 9.
如果始终不行，则可以使用fix ratio的方式，计算出合适的值填进去，只要通过DDR3稳定测试就可以。
