TI中文支持网Part Number:TDA3XEVM
TI专家好，
我们在拿自己做的TDA3x板子用CCS(10) Load Program时一直报如下错误（参考VisionSDK_UserGuide_TDA3xx.pdf），CCS Console里信息如下，错误信息：Cortex_M4_IPU1_C0: File Loader: Verification failed: Values at address 0x83500128 do not match Please verify target memory and memory map.
参照Data Verification Errors的说法像是TDA3x 启动的gel文件哪里寄存器地址映射不太对，请问这个具体怎么去修改gel配置文件呢？
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx Cortex M4 Startup Sequence In Progress… <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx Cortex M4 Startup Sequence DONE! <<<—
Cortex_M4_IPU1_C1: GEL Output: —>>> TDA3xx Cortex M4 Startup Sequence In Progress… <<<—
Cortex_M4_IPU1_C1: GEL Output: —>>> TDA3xx Cortex M4 Startup Sequence DONE! <<<—
ARP32_EVE_1: GEL Output: —>>> Configuring EVE Memory Map <<<—
ARP32_EVE_1: GEL Output: —>>> EVE Memory Map Done! <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx Target Connect Sequence Begins … <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> A device reset occurred <<<—
Cortex_M4_IPU1_C0: GEL Output: ==================================================
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx PG3.0 device detected =========
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx GP Device detected ===========
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx 15×15 Device detected ===========
Cortex_M4_IPU1_C0: GEL Output: ==================================================
Cortex_M4_IPU1_C0: GEL Output: Core Reset has occurred.
Cortex_M4_IPU1_C0: GEL Output: ==================================================
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx PG3.0 device detected =========
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx GP Device detected ===========
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx 15×15 Device detected ===========
Cortex_M4_IPU1_C0: GEL Output: ==================================================
Cortex_M4_IPU1_C0: GEL Output: —>>> All Control module lock registers are UNLOCKED <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> RTI is not currently enabled, so not doing anything <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> Starting IPU A-MMU configurations… <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> IPU A-MMU configuration completed. <<<—
Cortex_M4_IPU1_C0: GEL Output: ——————————————————————————————
Cortex_M4_IPU1_C0: GEL Output: —>>> DDR and DPLL configuration Based on Package selection pin status(Sysboot[7]) <<<—
Cortex_M4_IPU1_C0: GEL Output: ——————————————————————————————
Cortex_M4_IPU1_C0: GEL Output: —>>> 15×15 Package Detected(SYSBOOT[7]=0)… <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> PRCM Clock Configuration for OPPNOM in progress… <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> CORE DPLL OPP 0 clock config is in progress…
Cortex_M4_IPU1_C0: GEL Output: —>>> CORE DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C0: GEL Output: —>>> PER DPLL OPP 0 clock config in progress…
Cortex_M4_IPU1_C0: GEL Output: —>>> PER DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C0: GEL Output: —>>> DSP_GMAC DPLL OPP 0 clock config is in progress…
Cortex_M4_IPU1_C0: GEL Output: —>>> DSP_GMAC DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C0: GEL Output: —>>> EVE_VID_DSP DPLL OPP 0 clock config is in progress…
Cortex_M4_IPU1_C0: GEL Output: —>>> EVE_VID_DSP_DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C0: GEL Output: —>>> PRCM Clock Configuration for OPP 0 is DONE! <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> PRCM Configuration for all modules in progress… <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> PRCM Configuration for all modules is DONE! <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> DDR3 initialization starts (TI 15×15 EVM)… <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> DDR3 Initialization is in progress … <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> DDR DPLL clock config for 532MHz is in progress…
Cortex_M4_IPU1_C0: GEL Output: —>>> DDR DPLL clock config for 532MHz is in DONE!
Cortex_M4_IPU1_C0: GEL Output: Launch full leveling
Cortex_M4_IPU1_C0: GEL Output: Updating slave ratios in PHY_STATUSx registers
Cortex_M4_IPU1_C0: GEL Output: as per HW leveling output
Cortex_M4_IPU1_C0: GEL Output: HW leveling is now disabled. Using slave ratios fromCortex_M4_IPU1_C0: GEL Output: PHY_STATUSx registers
Cortex_M4_IPU1_C0: GEL Output: —>>> DDR3 532MHz Initialization is DONE! <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx Begin All Pad Configuration for Vision Platform <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx Begin All Pad Configuration for RGMII usage on EVM Platform <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx Begin GMAC_SW MDIO Pad Configuration <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx End GMAC_SW MDIO Pad Configuration <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx Begin GMAC_SW RGMII0 Pad Configuration <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx End GMAC_SW RGMII0 Pad Configuration <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx End All Pad Configuration for RGMII usage on EVM Platform <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx End All Pad Configuration for Vision Platform <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx Target Connect Sequence DONE !!!!! <<<—
Cortex_M4_IPU1_C0: GEL Output: !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
Cortex_M4_IPU1_C0: GEL Output: For STM based tracing on TI EVMs,Cortex_M4_IPU1_C0: GEL Output: run 'TDA3x EVM I2C EXPANDER CONTROL -> Enable_Trace_Pins()' function from Scripts menu on M4/CS_DAP_DebugSS
Cortex_M4_IPU1_C0: GEL Output: !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
Cortex_M4_IPU1_C0: GEL Output: Core Reset has occurred.
Cortex_M4_IPU1_C0: File Loader: Verification failed: Values at address 0x83500128 do not match Please verify target memory and memory map.
Cortex_M4_IPU1_C0: GEL: File: E:\ti\PROCESSOR_SDK_RADAR_03_08_00_00\vision_sdk\binaries_2243ES1.0-TDA3x\apps\tda3xx_evm_bios_radar\sbl\qspi_flash_writer\tda3xx-ar12-booster\qspi_flash_writer_ipu1_0_release.xem4: a data verification error occurred, file load failed.
此外，有时候断电重启板子和CCS也会出现如下的错误：Cortex_M4_IPU1_C0: Can't Run Target CPU: (Error -1268 @ 0x1090001) Device is locked up in Hard Fault or in NMI. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.2.0.00002)
麻烦帮忙看看出现这些问题的原因，该如何解决呢？非常感谢。
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx Cortex M4 Startup Sequence In Progress… <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx Cortex M4 Startup Sequence DONE! <<<—
Cortex_M4_IPU1_C1: GEL Output: —>>> TDA3xx Cortex M4 Startup Sequence In Progress… <<<—
Cortex_M4_IPU1_C1: GEL Output: —>>> TDA3xx Cortex M4 Startup Sequence DONE! <<<—
ARP32_EVE_1: GEL Output: —>>> Configuring EVE Memory Map <<<—
ARP32_EVE_1: GEL Output: —>>> EVE Memory Map Done! <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx Target Connect Sequence Begins … <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> A device reset occurred <<<—
Cortex_M4_IPU1_C0: GEL Output: ==================================================
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx PG3.0 device detected =========
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx GP Device detected ===========
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx 15×15 Device detected ===========
Cortex_M4_IPU1_C0: GEL Output: ==================================================
Cortex_M4_IPU1_C0: GEL Output: Core Reset has occurred.
Cortex_M4_IPU1_C0: GEL Output: ==================================================
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx PG3.0 device detected =========
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx GP Device detected ===========
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx 15×15 Device detected ===========
Cortex_M4_IPU1_C0: GEL Output: ==================================================
Cortex_M4_IPU1_C0: GEL Output: —>>> All Control module lock registers are UNLOCKED <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> RTI is not currently enabled, so not doing anything <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> Starting IPU A-MMU configurations… <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> IPU A-MMU configuration completed. <<<—
Cortex_M4_IPU1_C0: GEL Output: ——————————————————————————————
Cortex_M4_IPU1_C0: GEL Output: —>>> DDR and DPLL configuration Based on Package selection pin status(Sysboot[7]) <<<—
Cortex_M4_IPU1_C0: GEL Output: ——————————————————————————————
Cortex_M4_IPU1_C0: GEL Output: —>>> 15×15 Package Detected(SYSBOOT[7]=0)… <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> PRCM Clock Configuration for OPPNOM in progress… <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> CORE DPLL OPP 0 clock config is in progress…
Cortex_M4_IPU1_C0: GEL Output: —>>> CORE DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C0: GEL Output: —>>> PER DPLL OPP 0 clock config in progress…
Cortex_M4_IPU1_C0: GEL Output: —>>> PER DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C0: GEL Output: —>>> DSP_GMAC DPLL OPP 0 clock config is in progress…
Cortex_M4_IPU1_C0: GEL Output: —>>> DSP_GMAC DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C0: GEL Output: —>>> EVE_VID_DSP DPLL OPP 0 clock config is in progress…
Cortex_M4_IPU1_C0: GEL Output: —>>> EVE_VID_DSP_DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C0: GEL Output: —>>> PRCM Clock Configuration for OPP 0 is DONE! <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> PRCM Configuration for all modules in progress… <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> PRCM Configuration for all modules is DONE! <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> DDR3 initialization starts (TI 15×15 EVM)… <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> DDR3 Initialization is in progress … <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> DDR DPLL clock config for 532MHz is in progress…
Cortex_M4_IPU1_C0: GEL Output: —>>> DDR DPLL clock config for 532MHz is in DONE!
Cortex_M4_IPU1_C0: GEL Output: Launch full leveling
Cortex_M4_IPU1_C0: GEL Output: Updating slave ratios in PHY_STATUSx registers
Cortex_M4_IPU1_C0: GEL Output: as per HW leveling output
Cortex_M4_IPU1_C0: GEL Output: HW leveling is now disabled. Using slave ratios fromCortex_M4_IPU1_C0: GEL Output: PHY_STATUSx registers
Cortex_M4_IPU1_C0: GEL Output: —>>> DDR3 532MHz Initialization is DONE! <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx Begin All Pad Configuration for Vision Platform <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx Begin All Pad Configuration for RGMII usage on EVM Platform <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx Begin GMAC_SW MDIO Pad Configuration <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx End GMAC_SW MDIO Pad Configuration <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx Begin GMAC_SW RGMII0 Pad Configuration <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx End GMAC_SW RGMII0 Pad Configuration <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx End All Pad Configuration for RGMII usage on EVM Platform <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx End All Pad Configuration for Vision Platform <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx Target Connect Sequence DONE !!!!! <<<—
Cortex_M4_IPU1_C0: GEL Output: !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
Cortex_M4_IPU1_C0: GEL Output: For STM based tracing on TI EVMs,Cortex_M4_IPU1_C0: GEL Output: run 'TDA3x EVM I2C EXPANDER CONTROL -> Enable_Trace_Pins()' function from Scripts menu on M4/CS_DAP_DebugSS
Cortex_M4_IPU1_C0: GEL Output: !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
Cortex_M4_IPU1_C0: GEL Output: —>>> A device reset occurred <<<—
Cortex_M4_IPU1_C0: GEL Output: ==================================================
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx PG3.0 device detected =========
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx GP Device detected ===========
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx 15×15 Device detected ===========
Cortex_M4_IPU1_C0: GEL Output: ==================================================
Cortex_M4_IPU1_C0: GEL Output: Core Reset has occurred.
Cortex_M4_IPU1_C0: Can't Run Target CPU: (Error -1268 @ 0x1090001) Device is locked up in Hard Fault or in NMI. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.2.0.00002)
Cherry Zhou：
您好我们已收到您的问题并升级到英文论坛，因美国感恩节假期将近，预计答复时间将稍晚，敬请谅解！
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Kun Wang：
您好，
关于这个问题，我们的仿真器Blackhawk XDS560v2 System Trace 是通过60pin转14pin接到我们自己的开发板上的，请问这个地方需要修改啥接口配置文件、地址或寄存器之类的吗？通过CCS能连接上开发板，但是load program一直显示Values at address 0x83500128 do not match Please verify target memory and memory map。
谢谢。
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Cherry Zhou：
好的已经帮您反馈给工程师，如有新的消息会尽快给到您。
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Kun Wang：
非常感谢，我看这个问题划分到了电源管理模块，会不会TDAxx处理器相关工程师看不到啊，我们这个问题还挺急的，麻烦帮忙看下呗，感谢。
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Cherry Zhou：
抱歉负责该贴的工程师正在休假中，我们目前已发邮件反馈给另一位工程师，关于您的问题如有新的消息会尽快给到您。
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Kun Wang：
好的，非常感谢。
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Kun Wang：
您好，请问这个有更新吗？谢谢。
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Kun Wang：
您好，请问这个问题现在有更新吗？谢谢。
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Cherry Zhou：
很抱歉目前还没有新的信息，有新的消息会尽快给到您。
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YYF：
我目前的思路是调整下SYSBOOT15-0一共16个引脚的高低电平。您可以看下log中，SYSBOOT7是为0的，我怀疑可能SYSBOOT没有设置对。
正常debug模式应该是00111000 10000001。
目前我也遇到一样的问题，但我的SYSBOOT7引脚没拉出来，正在返修。不确定是不是因此引起，所以，咨询下您那边解决了吗？
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Kun Wang：
还没有啊，急死个人，debug模式00111000 10000001配置过，下面这些都试过，都会报错，不知道是不是自己的开发板，软件哪里配置或者寄存器地址啥的需要修改下，TDA2的EVM板用着都没啥问题。
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Kun Wang：
您好，
请问这个问题有更新吗，麻烦帮忙催下呗，卡了好久了，可能压根儿不是个大问题，麻烦相关工程师帮忙看下呗，定位个问题方向也行啊，谢谢。
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Cherry Zhou：
您好，非常抱歉，我们一直在跟进您的问题，但是由于工程师这边出了一些问题，导致目前还没有回复。我们已经跟进给团队的负责人，预计很快会有新的工程师来负责该问题。敬请谅解！
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Kun Wang：
好的，非常感谢，因为这个问题我们尝试了很多方法一直没有解决，所以有点急，非常感谢你们。
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Kun Wang：
您好，
我们这个处理板上采用的DDR总共是1G的，两片，我看官方开发板上应该是两片128M的，是不是这个地址分配及内存不对导致固件刷写的时候不知道往哪儿写入或者写入的地址不匹配才会出现“ File Loader: Verification failed: Values at address 0x83500128 do not match Please verify target memory and memory map.”以及”Can't Run Target CPU“这样的错误呢？
如果是的话，该如何去做修改呢？我看VisionSDK_UserGuide_MemoryMap.pdf里面针对TDA2x做的说明，跟TDA3x差异还挺大的，不知道对应的地址分配该如何设置，希望提供些方向，谢谢。
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Kun Wang：
您好，
请问你这边返修之后有验证结果吗，你们开发板上的DDR是和TI开发板上是一致的吗？
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YYF：
DDR我们用的是2片MT41K256M16TW-107 IT:P 没有再加ECC。这颗DDR地址线是A14-A0 15位的，我自己板子上没接。开发板上倒还预留了A15地址线。
返修后仍不行 现在会报两种问题 一种还是Device is locked up in Hard Fault or in NMI.从源汇编里面看是一直卡在205行，读CPSR寄存器会卡住。
另外一种现象和你类似 Values at address 0x8xxxxxxx do not match，不过这个0x8xxxxxxx地址我们每次开机都不一样
目前在根据EMIF Tools查DDR那块。
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Kun Wang：
您好，
请问这个问题有反馈吗？
目前我们怀疑就是DDR地址分配及内存不匹配的问题，编译的固件是按照开发板tda3xx_evm_bios_radar进行的，但是我们的DDR更换了IS43TR16256BL-107MBLI，1G的，参考过AM57x, DRA7x, and TDA2x EMIF Tools.pdf，还不太清楚这个要怎么去计算及修改DDR的寄存器那些，麻烦提供点方向，谢谢。
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Kun Wang：
那你们的问题应该跟我这是一样的，我们也是经常报这两个错误，我们用的两片IS43TR16256BL-107MBLI，官方用的MT41K128M16JT-125（128Mde ,16bits），参考过AM57x, DRA7x, and TDA2x EMIF Tools.pdf，还没太明白那个EMIF Tools怎么去计算的，如果你们有啥进展保持交流下呗，应该是一样的问题。
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Kun Wang：
您好，
请问你们有这个TI TDA3x开发板吗，有在这个开发板上做过验证吗，如果按照开发板上的DDR去Load是否可行呢？
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YYF：
没有上开发板 资金预算不够了。。
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Kun Wang：
哦哦，好的，我们也想在开发板上验证下，定位下问题，但是周期比较长，现在也在看EMIF Tools，保持沟通啊
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Cherry Zhou：
您好，十分抱歉让您久等了。工程师的回复如下：
Kun Wang 说：但是load program一直显示Values at address 0x83500128 do not match Please verify target memory and memory map。
这代表DDR配置不稳定。
假设这是在您自己的板子上完成的，那么建议您检查用于 DDR 初始化的 GEL script，因为它是独立于板子之外的。
用于 DDR 的 GEL 位于 C ： \ti\ccs1031\ccs\CCS_base\emulation\gel\TDA3x \TDA3xx_DDR_config.gel
请您先查看以上信息对您是否有帮助。
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Kun Wang：
非常感谢，应该就是DDR的内存、寄存器配置不匹配的问题，我们换了个DDR暂时可以用，但是之前的DDR应该也能用，就是要修改相关DDR的内存和地址，如果有用EMIF Tool修改相关寄存器gel地址等的指导就再好不过了，谢谢。
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Cherry Zhou：
嗯嗯好的，再帮您跟进给工程师问下这个问题，请您谅解由于我们的问题，答复时间可能会比预计时间长一些。再次抱歉！
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Kun Wang：
好的，非常感谢你们。
