SN75DP130 芯片应用问题

1.视频输入板卡->FPGA->视频输出板(DP130)->4K显示器，画面显示正常；

2.视频输入板卡->FPGA->视频输出板(DP130)->分析仪报错 link failed;

3.视频输入板卡->FPGA->视频输出板(DP130)->视频输入板(ITE6563+ITE68051), 无法识别；

4.FPGA测试程序，固定输出->视频输出板(DP130)->视频输入板(ITE6563+ITE68051), 画面显示正常；

怀疑时AUX通道造成的影响，请问该怎么定位问题，下面时DP130应用原理图

Amy Luo：

您好，
感谢您对TI产品的关注！为更加有效地解决您的问题，我需要询问更了解这款芯片的TI资深工程师，再为您解答，一旦得到回复会立即回复给您。

,

Amy Luo：

您好，感谢您的耐心
1. 请将电容 C123 由1uF 改为 0.22uF
2. 为什么使用 R73 和 R74? 是为了满足FPGA共模电压要求？
3. 是否有DP AUX分析仪来捕捉每种情况下的DP链路训练？
4. 是否也可以读取每种情况下的DP130 DPCD寄存器？

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dzjplay：

1.电容C123已改为0.22uF

2.R69、R70电阻已去掉

3.视频输出板(DP130)->视频输入板(ITE6563+ITE68051),读取AUX 数据如下表

   a)不清楚什么情况下会触发不停的read edid；

   b)另外视频输出板FGPA是以配置的参数固定输出时序，不使用EDID数据，那DP130屏蔽read edid操作吗

1
Set Power State: NORMAL (D0)

7
[DP_I2C] Start reading EDID

28
[DP_I2C] EDID Basic Block (KYS-9000P1_11)

56
[DP_I2C] EDID Extension Block (1: CEA-861)

58
[RX_CAP] Max_Link_Rate: HBR2 (5.4G)

59
[RX_CAP] Max_Lane_Count: 4

[RX_CAP] TPS3_SUPPORTED ; EN_FRAME_CAP

60
Set Power State: DOWN (D3)

62
[LINK_CONFIG] Link_Rate: HBR2 (5.4G)

64
[LINK_CONFIG] Lane_Count: 4 ; No Enhanced_Frame_EN

65
[RX_CAP] DP v1.4 ; No Downstream-Facing Port! ; Extended Receiver Capability field – Present

71
[LINK_CONFIG] Lane_Count: 4

72
Set Training Pattern: TPS1

73
Link Training: Clock Recovery… done

[SINK_STATUS] POST_LT_ADJ (LQA) done

74
Set Training Pattern: TPS3

75
Link Training: Done (HBR2 ; 4 lanes)

77
Training Pattern: Disabled

83
[DP_I2C] Start reading EDID

104
[DP_I2C] EDID Basic Block (KYS-9000P1_11)

110
[SINK_STATUS] Sink Count = 1 (CP_READY)

Link Training: None

117
[DP_I2C] Start reading EDID

138
[DP_I2C] EDID Basic Block (KYS-9000P1_11)

146
Set Power State: NORMAL (D0)

156
[DP_I2C] Start reading EDID

177
[DP_I2C] EDID Basic Block (KYS-9000P1_11)

184
Set Power State: DOWN (D3)

185
Set Power State: NORMAL (D0)

195
[DP_I2C] Start reading EDID

216
[DP_I2C] EDID Basic Block (KYS-9000P1_11)

223
Set Power State: DOWN (D3)

224
Set Power State: NORMAL (D0)

234
[DP_I2C] Start reading EDID

255
[DP_I2C] EDID Basic Block (KYS-9000P1_11)

262
Set Power State: DOWN (D3)

263
Set Power State: NORMAL (D0)

273
[DP_I2C] Start reading EDID

294
[DP_I2C] EDID Basic Block (KYS-9000P1_11)

301
Set Power State: DOWN (D3)

302
Set Power State: NORMAL (D0)

312
[DP_I2C] Start reading EDID

333
[DP_I2C] EDID Basic Block (KYS-9000P1_11)

340
Set Power State: DOWN (D3)

341
Set Power State: NORMAL (D0)

351
[DP_I2C] Start reading EDID

372
[DP_I2C] EDID Basic Block (KYS-9000P1_11)

379
Set Power State: DOWN (D3)

380
Set Power State: NORMAL (D0)

390
[DP_I2C] Start reading EDID

411
[DP_I2C] EDID Basic Block (KYS-9000P1_11)

418
Set Power State: DOWN (D3)

419
Set Power State: NORMAL (D0)

429
[DP_I2C] Start reading EDID

450
[DP_I2C] EDID Basic Block (KYS-9000P1_11)

457
Set Power State: DOWN (D3)

458
Set Power State: NORMAL (D0)

468
[DP_I2C] Start reading EDID

489
[DP_I2C] EDID Basic Block (KYS-9000P1_11)

496
Set Power State: DOWN (D3)

497
Set Power State: NORMAL (D0)

507
[DP_I2C] Start reading EDID

528
[DP_I2C] EDID Basic Block (KYS-9000P1_11)

535
Set Power State: DOWN (D3)

536
Set Power State: NORMAL (D0)

546
[DP_I2C] Start reading EDID

567
[DP_I2C] EDID Basic Block (KYS-9000P1_11)

574
Set Power State: DOWN (D3)

575
Set Power State: NORMAL (D0)

585
[DP_I2C] Start reading EDID

606
[DP_I2C] EDID Basic Block (KYS-9000P1_11)

613
Set Power State: DOWN (D3)

614
Set Power State: NORMAL (D0)

624
[DP_I2C] Start reading EDID

645
[DP_I2C] EDID Basic Block (KYS-9000P1_11)

652
Set Power State: DOWN (D3)

653
Set Power State: NORMAL (D0)

663
[DP_I2C] Start reading EDID

684
[DP_I2C] EDID Basic Block (KYS-9000P1_11)

691
Set Power State: DOWN (D3)

692
Set Power State: NORMAL (D0)

702
[DP_I2C] Start reading EDID

723
[DP_I2C] EDID Basic Block (KYS-9000P1_11)

730
Set Power State: DOWN (D3)

731
Set Power State: NORMAL (D0)

741
[DP_I2C] Start reading EDID

762
[DP_I2C] EDID Basic Block (KYS-9000P1_11)

769
Set Power State: DOWN (D3)

770
Set Power State: NORMAL (D0)

780
[DP_I2C] Start reading EDID

801
[DP_I2C] EDID Basic Block (KYS-9000P1_11)

808
Set Power State: DOWN (D3)

809
Set Power State: NORMAL (D0)

819
[DP_I2C] Start reading EDID

840
[DP_I2C] EDID Basic Block (KYS-9000P1_11)

847
Set Power State: DOWN (D3)

848
Set Power State: NORMAL (D0)

858
[DP_I2C] Start reading EDID

879
[DP_I2C] EDID Basic Block (KYS-9000P1_11)

886
Set Power State: DOWN (D3)

887
Set Power State: NORMAL (D0)

897
[DP_I2C] Start reading EDID

918
[DP_I2C] EDID Basic Block (KYS-9000P1_11)

925
Set Power State: DOWN (D3)

926
Set Power State: NORMAL (D0)

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Amy Luo：

您能拿一个万用表在交流耦合电容之前AUXP和AUXN上测量AUX 的共模电压吗？
对于DP130，交流耦合电容前的共模电压需要在0到2V之间。如果共模电压在范围内，DP130将只通过AUX 通信量。

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dzjplay：

测量电压0.02V左右

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Amy Luo：

R71是不是没有焊接，您可以焊接上R71吗
电路图中AUXP上是100k下拉、AUXN上是100k上拉，因此我预计AUXN上的电压大约为3V，您能再次检查AUXN共模电压测量值吗？

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dzjplay：

R71根据参考设计焊接了。
AUXN电压2.8V

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Amy Luo：

请确保CAD_SNK是低电平。AUXP约为0V，AUXN约为3V，那么DP130应该通过AUX数据。

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dzjplay：

上面已确认，下图是分析仪抓到的数据，请问Set power state: DOWN什么情况下会出现，这个command会导致重新training，这个命令会产生哪写影响

,

Amy Luo：

我在E2E论坛咨询的您的问题，我看到您有同时发帖，现在E2E论坛的工程师已经回复，请继续跟进，由E2E论坛的工程师为您提供更好的支持：
e2e.ti.com/…/3658241