TI中文支持网Part Number:ADS8686S
I'm debugging ads8686s and I'm having a problem. After the voltage signal is applied to the analog channel, I can read the data through the SPI port, but the read value will be much smaller than the actual value, which is only about 40% of the actual value. I measured the V (refcap) signal on pin 31, and it was only about 3.98v, which was too small; It is also measured that the voltage of the 52nd pin is 1.94v, which is slightly higher than the theoretical value of 1.89v; It is also measured that the voltage of the 70th pin is 1.91v, which is also slightly higher than the theoretical value of 1.87.
Kailyn Chen：
Hello, as to your questions, please confirm if the design meets the requirement of the datasheet description:
First, about the REFCAP, this pin must be decoupled to REFGND using a low equivalent series resistance (ESR), 10-µF ceramic capacitor. Place this capacitor as close to the REFCAP pin as possible. Do not drive any external load from this pin.
As to the REGCAPD, decouple this output pin separately to REGGNDD using a 10-µF capacitor. Place the capacitor close to the REGCAPD pin.
In addition, Decouple the digital LDO (DLDO) with a 10-µF capacitor between the REGCAPD and REGGNDD pins.
At last, the recommended sequence is to power up DVDD first, followed by AVDD. Hold RESET low until both supplies are stabilized.
Also, care should be attention to the pcb layout which is also the reason which could cause the incorrect voltage. Pleaser refer to the 10.1 Layout Guidelines section.
www.ti.com.cn/…/ads8686s.pdf
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Ming Jia：
I have confirmed that the decoupling capacitors are configured correctly, but the power on timing is not in accordance with your recommendation. At present, the 5V power supply is started first, then the CPU is started, and then the 3.3V power supply for peripheral power supply is started. Is this key to the ads8686s?
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Kailyn Chen：
Hello, ADS8686 has no strict power up sequence , but proper power up sequence is the basic of normally work.
The recommend power up sequence is to power up DVDD first, followed by AVDD.
If you power 5V first and then 3.3V , what about REST? It must hold RESET low until DVDD and AVDD are stabilized.
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Ming Jia：
I reset the ADC chip after the whole CPU system is powered on and works normally. By measuring the signal waveform, it is found that the reset problem can be basically eliminated. The following figure is the waveform of the data fitting I actually tested. From the shape in the figure, we can see that the signal shape is still correct, but the value is biased and small. The analog signal I actually applied is 50Hz / 0.3V, and the ADC analog channel range is 5V.
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Ming Jia：
The maximum code value I actually received is about 2756. There are differences between different channels, but the shape looks right.
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Ming Jia：
At present, I have tried software mode and hardware mode, and the results are almost the same without obvious difference. I also tried internal benchmarks and external benchmarks, and the results are similar. Anyway, the result is wrong.
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Ming Jia：
I think I've found the cause of the problem…The silk screen of the sample I got was "xds8686s", and I saw that the chip silk screen on the evaluation board I applied for was "ads8686s". I think there must be a difference between the two. After I removed the chip on the evaluation board and welded it to my own circuit board, the data I read was correct. Therefore, there may be some problems with the samples applied to me by TI's FAE in the early stage.
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Kailyn Chen：
Thank you for your feedback information.
