TI中文支持网Part Number:ADS42LB49Other Parts Discussed in Thread:LM97937,
您好，
请教一个关于overall latency 的问题
下图有个ADC的Overalllatency定义=ADClatency+tPDI.
ADC latency 是一个采样到最后输出的时间 ：典型值14个clock，也就是14*4=56ns
tPDI是时钟送入ADC到输出ADC的时间：典型值10.5ns，
我的疑问是：某个时刻250MHz时钟送入ADC，ADC是立刻开始采样模拟信号的吗？如果是的，那过了10.5ns时钟就会输出ADC，而第一个采样点需要56ns才输出，那overall latency应该是56ns，而不是手册上说的56+10.5=66.5ns。是我理解的哪里有问题？多谢！
Kailyn Chen：
您好,以LM97937为例,几个latency的定义:
Sample-to-Serial Out (S2SO) Latency—S2SO is the latency from when the signal is sampled at the ADC input until the sample appears in the serial stream at the ADC (TX) output.
Link Delay—Link delay is the delay from when the sampled parallel data is input to the serializer at the transmitter (ADC) until the same data is presented at the input to the elastic buffer.
Link Latency—Link latency is the latency from when the sampled parallel data is input to the serializer at the transmitter (ADC) until the same data is available in parallel form at the receiver.
Sample-to-Parallel Out (S2PO) Latency—S2PO is the latency from when the signal is sampled at the ADC input until the sample is released on the parallel bus at the receiving device (RX).
所以14个clock指的是从ADC采样到ADC输出的latency,而link latency指的是ADC输出数据到Serializer输入直到deserializer 解串出来的数据之间的延迟..
因此overall latency=ADC core latency+link latency=56ns+10.5ns=66.5ns.
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junjie fang1：
你发的这个ADC之后是串行数据，比较好理解。但是ADS42LB49的这个 tPDI 有点令人困惑。手册上说的是时钟送入ADC之后过10.5ns就会出现在输出时钟口上面，并不是ADC采样后的数据延迟。
按照你的说法，我这样的理解对不对？ 如果零时刻时钟送给ADC，那么10.5ns时刻输出时钟有信号，但是得到66.5ns时刻输出数据管脚才会有信号。那66.5ns之前数据管脚上的数据都是零吗？谢谢
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Kailyn Chen：
您好，抱歉回复晚了，tPDI指的是clock的输入输出传输延迟，参考datasheet中这个时序您看下：
