TI中文支持网Part Number:DAC37J82
Dears.
We need register values that match our setting.
The settings for using the DAC37J82 are shown below.
Input Clock : 500Mhz
Input Data rate : 500MSPS
Interpolation :2
Complex mixer enable
JESD LMFS : 4211
Internal PLL not use.
Please, Check
DacRegWrite(0x00, 0x0118);
DacRegWrite(0x01, 0x0003);
DacRegWrite(0x02, 0x2002);
DacRegWrite(0x03, 0xA300);
DacRegWrite(0x04, 0xF0F0);
DacRegWrite(0x05, 0xFF07);
DacRegWrite(0x06, 0xFFFF);
DacRegWrite(0x07, 0x3100);
DacRegWrite(0x08, 0x0000);
DacRegWrite(0x09, 0x0000);
DacRegWrite(0x0A, 0x0000);
DacRegWrite(0x0B, 0x0000);
DacRegWrite(0x0C, 0x0400);
DacRegWrite(0x0D, 0x0400);
DacRegWrite(0x0E, 0x0400);
DacRegWrite(0x0F, 0x0400);
DacRegWrite(0x10, 0x0000);
DacRegWrite(0x11, 0x0000);
DacRegWrite(0x12, 0x0000);
DacRegWrite(0x13, 0x0000);
DacRegWrite(0x14, 0x0000);
DacRegWrite(0x15, 0x0000);
DacRegWrite(0x16, 0x0000);
DacRegWrite(0x17, 0x0000);
DacRegWrite(0x18, 0x0000);
DacRegWrite(0x19, 0x0000);
DacRegWrite(0x4B, 0x1E00);
DacRegWrite(0x1B, 0x8000);
DacRegWrite(0x55, 0x00FF);
DacRegWrite(0x5F, 0x3210);
DacRegWrite(0x64, 0x0001);
DacRegWrite(0x22, 0x1B1B);
DacRegWrite(0x23, 0x01FF);
DacRegWrite(0x4A, 0x0F1E);
DacRegWrite(0x25, 0x4000);
DacRegWrite(0x26, 0x0000);
DacRegWrite(0x2D, 0x0001);
DacRegWrite(0x2E, 0xFFFF);
DacRegWrite(0x2F, 0x0004);
DacRegWrite(0x30, 0x0000);
DacRegWrite(0x4C, 0x1F03);
DacRegWrite(0x4D, 0x0100);
DacRegWrite(0x4E, 0x0F6F);
DacRegWrite(0x34, 0x0000);
DacRegWrite(0x3B, 0x0000);
DacRegWrite(0x3C, 0x1C28);
DacRegWrite(0x4F, 0x1C61);
DacRegWrite(0x5E, 0x0000);
DacRegWrite(0x59, 0x0000);
DacRegWrite(0x46, 0x1882);
DacRegWrite(0x5A, 0x00FF);
DacRegWrite(0x48, 0x3143);
DacRegWrite(0x5B, 0x00FF);
DacRegWrite(0x24, 0x0020);
DacRegWrite(0x1A, 0x0020);
DacRegWrite(0x31, 0x1000);
DacRegWrite(0x32, 0x0000);
DacRegWrite(0x33, 0x8828);
DacRegWrite(0x3D, 0x0088);
DacRegWrite(0x3E, 0x0128);
DacRegWrite(0x3F, 0x0000);
DacRegWrite(0x47, 0x01C8);
DacRegWrite(0x49, 0x0000);
DacRegWrite(0x58, 0x00FF);
DacRegWrite(0x60, 0x5764);
DacRegWrite(0x4D, 0x0100);
DacRegWrite(0x4E, 0x0F6F);
DacRegWrite(0x50, 0x0000);
DacRegWrite(0x51, 0x00DC);
DacRegWrite(0x52, 0x00FF);
DacRegWrite(0x53, 0x0000);
DacRegWrite(0x54, 0x00FC);
DacRegWrite(0x5C, 0x1111);
DacRegWrite(0x61, 0x0111);
DacRegWrite(0x1E, 0x9999);
DacRegWrite(0x1F, 0x9980);
DacRegWrite(0x20, 0x8008);
DacRegWrite(0x65, 0x0001);
DacRegWrite(0x66, 0x0001);
DacRegWrite(0x67, 0x0001);
DacRegWrite(0x68, 0x7709);
DacRegWrite(0x69, 0x0000);
DacRegWrite(0x6A, 0x0000);
DacRegWrite(0x6B, 0xBD07);
DacRegWrite(0x6C, 0x0007);
DacRegWrite(0x6D, 0x0090);
DacRegWrite(0x6E, 0x0000);
DacRegWrite(0x6F, 0x0000);
DacRegWrite(0x70, 0x0000);
DacRegWrite(0x71, 0x0000);
DacRegWrite(0x72, 0x0000);
DacRegWrite(0x73, 0x0000);
DacRegWrite(0x74, 0x0000);
DacRegWrite(0x75, 0x0000);
DacRegWrite(0x76, 0x0000);
DacRegWrite(0x77, 0x0000);
DacRegWrite(0x78, 0x0000);
DacRegWrite(0x79, 0x0000);
DacRegWrite(0x7A, 0x0000);
DacRegWrite(0x7B, 0x0000);
DacRegWrite(0x7C, 0x0000);
DacRegWrite(0x7D, 0x0000);
DacRegWrite(0x3B, 0x0000);
DacRegWrite(0x25, 0x0000);
DacRegWrite(0x3C, 0x0250);
DacRegWrite(0x3C, 0x0250);
DacRegWrite(0x3E, 0x0128);
DacRegWrite(0x4C, 0x1F03);
DacRegWrite(0x4D, 0x0100);
DacRegWrite(0x4B, 0x1E00);
DacRegWrite(0x56, 0x0000);
DacRegWrite(0x57, 0x00FF);
DacRegWrite(0x00, 0x0018); DacRegWrite(0x4A, 0x0F1E);
DacRegWrite(0x4A, 0x0F1E);
DacRegWrite(0x4A, 0x0F1E);
DacRegWrite(0x4A, 0x0F01);
DacRegWrite(0x4A, 0x0F1F);
DacRegWrite(0x4A, 0x0F01);
DacRegWrite(0x03, 0xF081);
Thank you.
Amy Luo：
您好，
目前输出是什么现象？有哪些异常现象
,
user4672275：
目前的现象是输出波形不是正弦波，同时，改变输入参数波形也没有变化。serdes pll显示已锁定，读取FIFO的状态alarm寄存器，显示FIFO读取为空。请问我这个配置参数和配置顺序是否正确呢？
,
Amy Luo：
data rate必须是sample rate / interpolation 因子，发送数据的速率应该是250Msps而不是500Msps 。随附的一些信息将有助于JESD204B，这是最新的高速ADC和DAC的使用，以及DAC37J82配置文件，该文件是用EVM根据您的设置配置的。
7140.JESD204B Overview – May 2018.pptx
JESD204B Tools debug and tips .pptx
4211_Fs_500_2x_int.cfg
,
yang jing：
您好，感谢您的回答
我们的DAC的输入是通过JESD204B TX的xilinx官方例程发送的， 4 LANE 参考时钟为125M，所以我们设置的INPUT DATA RATE才会是500M， 但是在DAC GUI 界面 如果我设置INPUT DATA RATE = 500M, 4 LANE 的话 我的插值大小不能为4， 报错为maximum DAC output rate is 1600MSPS, 所以我们这里设置的差值才会是2。
,
Amy Luo：
必须遵循以下规则：DAC data rate = DAC采样时钟除以插值速率。DAC对输入数据的采样速度有限制。这与几个因素有关。如果您计划以500MHz的频率向DAC发送数据并使用2x插值，DAC时钟必须为1GHz。
,
user4672275：
好的，那能否帮我们配置一下，我们中频输出为100M信号，输出给DAC的时钟为500M，DAC的线速率为5Gbps，数据刷新率为500MSPS，FPGA端的时钟为125M。不适用DAC内部的PLL。
,
Amy Luo：
使用LMFS=4211、interpolation =1x、K=20 和 SYSREF=3.125MHz。FPGA参考时钟=125MHz，lane serdes rate是5Gsps。附件是此的DAC配置文件
4211_Fs_500_1x_Int.cfg
,
yang jing：
您好，感谢您的回复，我们按照您所发的配置文件进行DAC的配置，但是依旧没有得到期望的结果，您是否能帮我检查一下我的JESD204B IP核是否配置正确，截图如下
同时附上我们烧好程序过后的ILA截图
下面两张 第一张是检查fifo alarm的， 第二张是检测pll锁定的
最后一张是来自示波器显示的波形
期待您的回复！
,
Amy Luo：
让客户根据所附文件加载寄存器，并验证它们是否可以获得20MHz输出音调。在加载寄存器之前，确保DAC具有500MHz时钟并且DAC接收到硬复位。这将检查SPI、设备电源和设备输入时钟。如果能做到这一点，可以继续讨论JESD接口问题。
NCO_test_no_LMK_20MHz.cfg
,
user4672275：
是不是回复错误了？
,
Amy Luo：
抱歉，这个是我问的TI的其他同事，他给回复的，我忘记改称呼了，没有回复错误。
