TI中文支持网#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
// ADC start parameters
#if (CPU_FRQ_150MHZ) // Default – 150 MHz SYSCLKOUT
#define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25.0 MHz
#endif
#if (CPU_FRQ_100MHZ)
#define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2) = 25.0 MHz
#endif
#define ADC_CKPS 0x1 // ADC module clock = HSPCLK/2*ADC_CKPS = 25.0MHz/(1*2) = 12.5MHz
#define ADC_SHCLK 0xf // S/H width in ADC module periods = 16 ADC clocks
#define AVG 1000 // Average sample limit
#define BUF_SIZE 20 // Sample buffer size
// Global variable for this example
Uint16 j=0;
#pragma DATA_SECTION(DMABuf1,"DMARAML4");
volatile Uint16 DMABuf1[20];
volatile Uint16 *DMADest;
volatile Uint16 *DMASource;
interrupt void local_DINTCH1_ISR(void);
void main(void)
{
Uint16 i;
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the DSP2833x_SysCtrl.c file.
InitSysCtrl();
// Specific clock setting for this example:
EALLOW;
SysCtrlRegs.HISPCP.all = ADC_MODCLK; // HSPCLK = SYSCLKOUT/ADC_MODCLK
EDIS;
// Step 2. Initialize GPIO:
// This example function is found in the DSP2833x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio(); // Skipped for this example
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the DSP2833x_PieCtrl.c file.
InitPieCtrl();
// Clear Table
for (i=0; i<BUF_SIZE; i++)
{
DMABuf1[i] = 0;
}
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
// This function is found in DSP2833x_PieVect.c.
InitPieVectTable();
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
EALLOW; // Allow access to EALLOW protected registers
PieVectTable.DINTCH1= &local_DINTCH1_ISR;
EDIS; // Disable access to EALLOW protected registers
IER = M_INT7 ; //Enable INT7 (7.1 DMA Ch1)
EnableInterrupts();
// Step 4. Initialize all the Device Peripherals:
// This function is found in DSP2833x_InitPeripherals.c
// InitPeripherals(); // Not required for this example
InitAdc(); // For this example, init the ADC
// Specific ADC setup for this example:
AdcRegs.ADCTRL1.bit.ACQ_PS = ADC_SHCLK;
AdcRegs.ADCTRL3.bit.ADCCLKPS = ADC_CKPS;
AdcRegs.ADCTRL1.bit.SEQ_CASC = 0; // 0 Non-Cascaded Mode
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1;
AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1;// Enable SOCA from ePWM to start SEQ1
AdcRegs.ADCTRL2.bit.RST_SEQ1 = 0x1;
AdcRegs.ADCCHSELSEQ1.bit.CONV00 =0x0; //only one channel is slected
AdcRegs.ADCCHSELSEQ1.bit.CONV01 =0x0;
AdcRegs.ADCCHSELSEQ1.bit.CONV02 =0x0;
AdcRegs.ADCCHSELSEQ1.bit.CONV03 =0x0;
AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 3; // Set up ADC to perform 4 conversions for every SOC
// Assumes ePWM1 clock is already enabled in InitSysCtrl();
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC from from CPMA on upcount
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm1Regs.CMPA.half.CMPA = 150; // Set compare A value
EPwm1Regs.TBPRD = 750; // Set period for ePWM1 —0.05ms
EPwm1Regs.TBCTL.bit.CTRMODE = 0; // count up and start//Step 5. User specific code, enable interrupts:
// Initialize DMA DMAInitialize();
// Configure DMA Channel
DMADest = &DMABuf1[0]; //Point DMA destination to the beginning of the array
DMASource = &AdcMirror.ADCRESULT0; //Point DMA source to ADC result register base
DMACH1AddrConfig(DMADest,DMASource);
DMACH1BurstConfig(3,1,4); //burst 4words;SRC+1,DST+4;
DMACH1TransferConfig(4,0,4); //5 bursts,SRC+0,DST+4;
DMACH1WrapConfig(0,0,0,1); //SRC wrap around after 1 burst,SRC+0;DST wrap around after 1 burst,DST+1;
DMACH1ModeConfig(DMA_SEQ1INT,PERINT_ENABLE,ONESHOT_DISABLE,CONT_ENABLE,SYNC_DISABLE,SYNC_SRC,
OVRFLOW_DISABLE,SIXTEEN_BIT,CHINT_END,CHINT_ENABLE);
StartDMACH1();
while(1);
// Start SEQ1
// AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0x1;
//for(i=0;i<10;i++){
// for(j=0;j<1000;j++){}
// AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 1; //Normally ADC will be tied to ePWM, or timed routine
// } //For this example will re-start manually
}
// INT7.1
interrupt void local_DINTCH1_ISR(void) // DMA Channel 1
{
//20个数据处理，每隔0.0025ms采集一次
//总共用时0.1ms
// To receive more interrupts from this PIE group, acknowledge this interrupt PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
}
而且，TI提供的例程，同样的结果，也是DMA对应的目标内存地址的数据不对
Eric Ma：
zhang lei,
那个cmd文件你用的是TI的吗，即DMARAML4段是映射到RAML4 : origin = 0x00C000, length = 0x001000 。
你在调试的时候观察一下AdcMirror.ADCRESULT0这个数据对不对，确保在搬运之前这个数据是对的。
你用下面的例程测试一下。
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
// ADC start parameters
#if (CPU_FRQ_150MHZ) // Default – 150 MHz SYSCLKOUT
#define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25.0 MHz
#endif
#if (CPU_FRQ_100MHZ)
#define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2) = 25.0 MHz
#endif
#define ADC_CKPS 0x1 // ADC module clock = HSPCLK/2*ADC_CKPS = 25.0MHz/(1*2) = 12.5MHz
#define ADC_SHCLK 0xf // S/H width in ADC module periods = 16 ADC clocks
#define AVG 1000 // Average sample limit
#define BUF_SIZE 20 // Sample buffer size
// Global variable for this example
Uint16 j=0;
#pragma DATA_SECTION(DMABuf1,"DMARAML4");
volatile Uint16 DMABuf1[20];
volatile Uint16 *DMADest;
volatile Uint16 *DMASource;
interrupt void local_DINTCH1_ISR(void);
void main(void)
{
Uint16 i;
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the DSP2833x_SysCtrl.c file.
InitSysCtrl();
// Specific clock setting for this example:
EALLOW;
SysCtrlRegs.HISPCP.all = ADC_MODCLK; // HSPCLK = SYSCLKOUT/ADC_MODCLK
EDIS;
// Step 2. Initialize GPIO:
// This example function is found in the DSP2833x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio(); // Skipped for this example
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the DSP2833x_PieCtrl.c file.
InitPieCtrl();
// Clear Table
for (i=0; i<BUF_SIZE; i++)
{
DMABuf1[i] = 0;
}
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
// This function is found in DSP2833x_PieVect.c.
InitPieVectTable();
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
EALLOW; // Allow access to EALLOW protected registers
PieVectTable.DINTCH1= &local_DINTCH1_ISR;
EDIS; // Disable access to EALLOW protected registers
IER = M_INT7 ; //Enable INT7 (7.1 DMA Ch1)
EnableInterrupts();
// Step 4. Initialize all the Device Peripherals:
// This function is found in DSP2833x_InitPeripherals.c
// InitPeripherals(); // Not required for this example
InitAdc(); // For this example, init the ADC
// Specific ADC setup for this example:
AdcRegs.ADCTRL1.bit.ACQ_PS = ADC_SHCLK;
AdcRegs.ADCTRL3.bit.ADCCLKPS = ADC_CKPS;
AdcRegs.ADCTRL1.bit.SEQ_CASC = 0; // 0 Non-Cascaded Mode
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1;
AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1;// Enable SOCA from ePWM to start SEQ1
AdcRegs.ADCTRL2.bit.RST_SEQ1 = 0x1;
AdcRegs.ADCCHSELSEQ1.bit.CONV00 =0x0; //only one channel is slected
AdcRegs.ADCCHSELSEQ1.bit.CONV01 =0x0;
AdcRegs.ADCCHSELSEQ1.bit.CONV02 =0x0;
AdcRegs.ADCCHSELSEQ1.bit.CONV03 =0x0;
AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 3; // Set up ADC to perform 4 conversions for every SOC
// Assumes ePWM1 clock is already enabled in InitSysCtrl();
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC from from CPMA on upcount
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm1Regs.CMPA.half.CMPA = 150; // Set compare A value
EPwm1Regs.TBPRD = 750; // Set period for ePWM1 —0.05ms
EPwm1Regs.TBCTL.bit.CTRMODE = 0; // count up and start//Step 5. User specific code, enable interrupts:
// Initialize DMA DMAInitialize();
// Configure DMA Channel
DMADest = &DMABuf1[0]; //Point DMA destination to the beginning of the array
DMASource = &AdcMirror.ADCRESULT0; //Point DMA source to ADC result register base
DMACH1AddrConfig(DMADest,DMASource);
DMACH1BurstConfig(3,1,4); //burst 4words;SRC+1,DST+4;
DMACH1TransferConfig(4,0,4); //5 bursts,SRC+0,DST+4;
DMACH1WrapConfig(0,0,0,1); //SRC wrap around after 1 burst,SRC+0;DST wrap around after 1 burst,DST+1;
DMACH1ModeConfig(DMA_SEQ1INT,PERINT_ENABLE,ONESHOT_DISABLE,CONT_ENABLE,SYNC_DISABLE,SYNC_SRC,
OVRFLOW_DISABLE,SIXTEEN_BIT,CHINT_END,CHINT_ENABLE);
StartDMACH1();
while(1);
// Start SEQ1
// AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0x1;
//for(i=0;i<10;i++){
// for(j=0;j<1000;j++){}
// AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 1; //Normally ADC will be tied to ePWM, or timed routine
// } //For this example will re-start manually
}
// INT7.1
interrupt void local_DINTCH1_ISR(void) // DMA Channel 1
{
//20个数据处理，每隔0.0025ms采集一次
//总共用时0.1ms
// To receive more interrupts from this PIE group, acknowledge this interrupt PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
}
而且，TI提供的例程，同样的结果，也是DMA对应的目标内存地址的数据不对
Eric Ma：
回复 Eric Ma:
附件
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
// ADC start parameters
#if (CPU_FRQ_150MHZ) // Default – 150 MHz SYSCLKOUT
#define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25.0 MHz
#endif
#if (CPU_FRQ_100MHZ)
#define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2) = 25.0 MHz
#endif
#define ADC_CKPS 0x1 // ADC module clock = HSPCLK/2*ADC_CKPS = 25.0MHz/(1*2) = 12.5MHz
#define ADC_SHCLK 0xf // S/H width in ADC module periods = 16 ADC clocks
#define AVG 1000 // Average sample limit
#define BUF_SIZE 20 // Sample buffer size
// Global variable for this example
Uint16 j=0;
#pragma DATA_SECTION(DMABuf1,"DMARAML4");
volatile Uint16 DMABuf1[20];
volatile Uint16 *DMADest;
volatile Uint16 *DMASource;
interrupt void local_DINTCH1_ISR(void);
void main(void)
{
Uint16 i;
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the DSP2833x_SysCtrl.c file.
InitSysCtrl();
// Specific clock setting for this example:
EALLOW;
SysCtrlRegs.HISPCP.all = ADC_MODCLK; // HSPCLK = SYSCLKOUT/ADC_MODCLK
EDIS;
// Step 2. Initialize GPIO:
// This example function is found in the DSP2833x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio(); // Skipped for this example
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the DSP2833x_PieCtrl.c file.
InitPieCtrl();
// Clear Table
for (i=0; i<BUF_SIZE; i++)
{
DMABuf1[i] = 0;
}
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
// This function is found in DSP2833x_PieVect.c.
InitPieVectTable();
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
EALLOW; // Allow access to EALLOW protected registers
PieVectTable.DINTCH1= &local_DINTCH1_ISR;
EDIS; // Disable access to EALLOW protected registers
IER = M_INT7 ; //Enable INT7 (7.1 DMA Ch1)
EnableInterrupts();
// Step 4. Initialize all the Device Peripherals:
// This function is found in DSP2833x_InitPeripherals.c
// InitPeripherals(); // Not required for this example
InitAdc(); // For this example, init the ADC
// Specific ADC setup for this example:
AdcRegs.ADCTRL1.bit.ACQ_PS = ADC_SHCLK;
AdcRegs.ADCTRL3.bit.ADCCLKPS = ADC_CKPS;
AdcRegs.ADCTRL1.bit.SEQ_CASC = 0; // 0 Non-Cascaded Mode
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1;
AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1;// Enable SOCA from ePWM to start SEQ1
AdcRegs.ADCTRL2.bit.RST_SEQ1 = 0x1;
AdcRegs.ADCCHSELSEQ1.bit.CONV00 =0x0; //only one channel is slected
AdcRegs.ADCCHSELSEQ1.bit.CONV01 =0x0;
AdcRegs.ADCCHSELSEQ1.bit.CONV02 =0x0;
AdcRegs.ADCCHSELSEQ1.bit.CONV03 =0x0;
AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 3; // Set up ADC to perform 4 conversions for every SOC
// Assumes ePWM1 clock is already enabled in InitSysCtrl();
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC from from CPMA on upcount
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm1Regs.CMPA.half.CMPA = 150; // Set compare A value
EPwm1Regs.TBPRD = 750; // Set period for ePWM1 —0.05ms
EPwm1Regs.TBCTL.bit.CTRMODE = 0; // count up and start//Step 5. User specific code, enable interrupts:
// Initialize DMA DMAInitialize();
// Configure DMA Channel
DMADest = &DMABuf1[0]; //Point DMA destination to the beginning of the array
DMASource = &AdcMirror.ADCRESULT0; //Point DMA source to ADC result register base
DMACH1AddrConfig(DMADest,DMASource);
DMACH1BurstConfig(3,1,4); //burst 4words;SRC+1,DST+4;
DMACH1TransferConfig(4,0,4); //5 bursts,SRC+0,DST+4;
DMACH1WrapConfig(0,0,0,1); //SRC wrap around after 1 burst,SRC+0;DST wrap around after 1 burst,DST+1;
DMACH1ModeConfig(DMA_SEQ1INT,PERINT_ENABLE,ONESHOT_DISABLE,CONT_ENABLE,SYNC_DISABLE,SYNC_SRC,
OVRFLOW_DISABLE,SIXTEEN_BIT,CHINT_END,CHINT_ENABLE);
StartDMACH1();
while(1);
// Start SEQ1
// AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0x1;
//for(i=0;i<10;i++){
// for(j=0;j<1000;j++){}
// AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 1; //Normally ADC will be tied to ePWM, or timed routine
// } //For this example will re-start manually
}
// INT7.1
interrupt void local_DINTCH1_ISR(void) // DMA Channel 1
{
//20个数据处理，每隔0.0025ms采集一次
//总共用时0.1ms
// To receive more interrupts from this PIE group, acknowledge this interrupt PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
}
而且，TI提供的例程，同样的结果，也是DMA对应的目标内存地址的数据不对
yang jiao：
回复 Eric Ma:
您好，我也写了一段ADC-DMA的程序，大问题应该没有了，就是采集的数据还是不正确，DMA的设置我就是按照您这个程序写的，如果单步运行的话，程序能过去，如果全速运行就不行，就会停在 if(AD_Flag) 的后面那行，实在不知道为什么了
#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
//B2,B4,B6,B8,B10=1#define U54 GpioDataRegs.GPBDAT.bit.GPIO54 #define U56 GpioDataRegs.GPBDAT.bit.GPIO56 #define U58 GpioDataRegs.GPBDAT.bit.GPIO58 #define U60 GpioDataRegs.GPBDAT.bit.GPIO60
//B1,B3,B5,B7,B9=0#define U55 GpioDataRegs.GPBDAT.bit.GPIO55 #define U57 GpioDataRegs.GPBDAT.bit.GPIO57 #define U59 GpioDataRegs.GPBDAT.bit.GPIO59 #define U61 GpioDataRegs.GPBDAT.bit.GPIO61
#define LED1 GpioDataRegs.GPBDAT.bit.GPIO50 // For test LED1#define LED2 GpioDataRegs.GPBDAT.bit.GPIO49 // For test LED2#define SLAVE#define NOP asm(" nop")#define IO_NOP NOP;NOP;NOP;NOP
// ADC start parameters#if (CPU_FRQ_150MHZ) // Default – 150 MHz SYSCLKOUT #define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25.0 MHz#endif#if (CPU_FRQ_100MHZ) #define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2) = 25.0 MHz#endif#define ADC_CKPS 0x5 // ADC module clock = HSPCLK/1 = 25.5MHz/(1) = 25.0 MHz#define ADC_SHCLK 0x7 // S/H width in ADC module periods = 2 ADC cycle
#define CPU_FREQ 150E6#define LSPCLK_FREQ CPU_FREQ/4#define SCI_FREQ 115200#define SCI_PRD (LSPCLK_FREQ/(SCI_FREQ*8))-1 // 115200 bps
#define BUF_SIZE 128 // Sample buffer size#define DMA_SIZE (BUF_SIZE/16)-1
volatile Uint16 *DMADest;volatile Uint16 *DMASource;
extern Uint16 RamfuncsLoadStart;extern Uint16 RamfuncsLoadEnd;extern Uint16 RamfuncsRunStart;
interrupt void local_DINTCH1_ISR(void);interrupt void scibTxFifoIsr(void);interrupt void scibRxFifoIsr(void);
void error(void);void spi_ctrlio_init(void);void InitScibGpio(void);
void scib_fifo_init(void);void adc_config(void);void dma_config(void);
volatile Uint16 DMABuf1[BUF_SIZE];#pragma DATA_SECTION(DMABuf1,"DMARAML4");
//Uint16 buffer1[BUF_SIZE];Uint16 RX_buffer[8];volatile char TX_Buffer[8];volatile char *display;volatile Uint32 j;
volatile Uint16 AD_Flag = 0;volatile Uint16 Run_Flag = 0;volatile Uint16 Motor1_3NM = 60;
void main(void){ Uint16 i,j=0; Uint32 temp; display = TX_Buffer;// Step 1. Initialize System Control:// PLL, WatchDog, enable Peripheral Clocks// This example function is found in the DSP2833x_SysCtrl.c file. InitSysCtrl();
// Specific clock setting for this example: EALLOW; SysCtrlRegs.HISPCP.all = ADC_MODCLK; // HSPCLK = SYSCLKOUT/2*ADC_MODCLK EDIS; spi_ctrlio_init();
//the eight IO state
InitScibGpio();
// Step 3. Clear all interrupts and initialize PIE vector table:// Disable CPU interrupts DINT;
// Initialize the PIE control registers to their default state.// The default state is all PIE interrupts disabled and flags// are cleared.// This function is found in the DSP2833x_PieCtrl.c file. InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags: IER = 0x0000; IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt// Service Routines (ISR).// This will populate the entire table, even if the interrupt// is not used in this example. This is useful for debug purposes.// The shell ISR routines are found in DSP2833x_DefaultIsr.c.// This function is found in DSP2833x_PieVect.c. InitPieVectTable(); MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart); InitFlash(); EALLOW; // Allow access to EALLOW protected registers PieVectTable.DINTCH1= &local_DINTCH1_ISR; PieVectTable.SCIRXINTB = &scibRxFifoIsr; PieVectTable.SCITXINTB = &scibTxFifoIsr; EDIS; // Disable access to EALLOW protected registers scib_fifo_init(); IER |= M_INT1; IER |= M_INT7; IER |= M_INT9; IER |= M_INT13; IER |= M_INT14; // Enable TINT0 in the PIE: Group 1 interrupt 7 PieCtrlRegs.PIEIER1.bit.INTx7 = 1; PieCtrlRegs.PIEIER7.bit.INTx1 = 1; PieCtrlRegs.PIEIER9.bit.INTx3 = 1; // PIE Group 9, INT3// PieCtrlRegs.PIEIER9.bit.INTx4 = 1; // PIE Group 9, INT4 // EnableInterrupts(); // Enable global Interrupts and higher priority real-time debug events: EINT; // Enable Global interrupt INTM // ERTM; // Enable Global realtime interrupt DBGM // Initialize DMA InitAdc(); // For this example, init the ADC adc_config();
DMAInitialize(); dma_config();
LED1 = 1; IO_NOP; IO_NOP; IO_NOP; IO_NOP; IO_NOP; IO_NOP; U54=1; IO_NOP; IO_NOP; IO_NOP; IO_NOP; IO_NOP; IO_NOP; U56=1; IO_NOP; IO_NOP; IO_NOP; IO_NOP; IO_NOP; IO_NOP; U58=1; IO_NOP; IO_NOP; IO_NOP; IO_NOP; IO_NOP; IO_NOP; IO_NOP; U60=1; IO_NOP; IO_NOP; IO_NOP; IO_NOP; IO_NOP; IO_NOP; IO_NOP; U55=0; IO_NOP; IO_NOP; IO_NOP; IO_NOP; IO_NOP; IO_NOP; U57=0; IO_NOP; U59=0; IO_NOP; U61=0; IO_NOP; // Clear Table for (i=0; i<BUF_SIZE; i++) DMABuf1[i] = 0; for(i=0;i<8;i++) RX_buffer[i] = 0; // Read data// for(i=0;i<BUF_SIZE;i++)// buffer1[i]=0; for(;;){ AdcRegs.ADCCHSELSEQ1.all = 0x8888; // Initialize all ADC0 channel selects to B0 AdcRegs.ADCCHSELSEQ2.all = 0x8888; AdcRegs.ADCCHSELSEQ3.all = 0x8888; AdcRegs.ADCCHSELSEQ4.all = 0x8888; StartDMACH1(); // Start DMA AdcRegs.ADCTRL2.bit.RST_SEQ1 = 0x1; AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0x1; // Start SEQ1 AD_Flag = 1; //do not use the local_DINTCH1_ISR // for(i=0;i<1000;i++) // for(j=0;j<100;j++); if(AD_Flag){ // AD0 feedbake control, 3NM // for(i=0;i<16;i++){ // buffer1[i]=DMABuf1[i]; // } for(i=0;i<16;i++) j += DMABuf1[i]; j = j/16; if((j >= Motor1_3NM )&&( Run_Flag)){ AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0x0; LED1 = 0; IO_NOP; IO_NOP; IO_NOP; IO_NOP; IO_NOP; U54=0; IO_NOP; IO_NOP; IO_NOP; IO_NOP; IO_NOP; U56=0; IO_NOP; IO_NOP; IO_NOP; IO_NOP; IO_NOP; U58=0; IO_NOP; IO_NOP; IO_NOP; IO_NOP; IO_NOP; IO_NOP; U60=0; IO_NOP; IO_NOP; IO_NOP;IO_NOP; IO_NOP; U55=1; IO_NOP; IO_NOP; IO_NOP; IO_NOP; U57=1; IO_NOP; IO_NOP; IO_NOP; IO_NOP; IO_NOP; U59=1; IO_NOP; IO_NOP; IO_NOP; IO_NOP; IO_NOP; U61=1; IO_NOP; IO_NOP; IO_NOP; IO_NOP; IO_NOP; if(Run_Flag){ display[0] = 0x00BB; display[1] = 0x0060; display[2] = 0x0000; display[3] = 0x0000; display[4] = 0x0000; display[5] = 0x0000; display[6] = 0x0000; temp = 0; for(j=0;j<7;j++){ for(i=0;i<8;i++){ temp = temp + ((display[j]>>i)&0x01); } } display[7] = temp; } PieCtrlRegs.PIEIER9.bit.INTx4 = 1; // Send messege } else StartDMACH1(); AD_Flag = 0; } }}// INT7.1interrupt void local_DINTCH1_ISR(void) // DMA Channel 1{ AD_Flag = 1;// asm (" ESTOP0"); GpioDataRegs.GPBDAT.bit.GPIO63 = ~GpioDataRegs.GPBDAT.bit.GPIO63; /* DMACH1AddrConfig(DMADest,DMASource); DMACH1BurstConfig(15,1,1); DMACH1TransferConfig(DMA_SIZE,-15,1); DMACH1WrapConfig(66,0,66,16); DMACH1ModeConfig(DMA_SEQ1INT,PERINT_ENABLE,ONESHOT_DISABLE,CONT_DISABLE,SYNC_DISABLE,SYNC_SRC, OVRFLOW_DISABLE,SIXTEEN_BIT,CHINT_END,CHINT_ENABLE); */// StartDMACH1(); // To receive more interrupts from this PIE group, acknowledge this interrupt PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; // Next two lines for debug only to halt the processor here // Remove after inserting ISR Code
// for(;;);}
interrupt void scibTxFifoIsr(void){ Uint16 i;
PieCtrlRegs.PIEIER9.bit.INTx4 = 0;
for(i=0; i< 8; i++) { ScibRegs.SCITXBUF=display[i]; // Send data }/* for(i=0; i< 8; i++) //Increment send data for next cycle { sdataB[i] = (sdataB[i]-1) & 0x00FF; }*/ ScibRegs.SCIFFTX.bit.TXFFINTCLR=1; // Clear Interrupt flag PieCtrlRegs.PIEACK.all|=0x100; // Issue PIE ACK = CPU INT9 for(i=0; i< 8; i++) { ScibRegs.SCITXBUF=0; }}
interrupt void scibRxFifoIsr(void){ Uint16 i,j,temp1; for(i=0;i<8;i++) RX_buffer[i] = ScibRegs.SCIRXBUF.all; // Read data Motor1_3NM = (RX_buffer[2]*256 + RX_buffer[3]); temp1 = 0; for(j=0;j<7;j++){ for(i=0;i<8;i++){ temp1 = temp1 + ((RX_buffer[j]>>i)&0x01); } } if(temp1 == RX_buffer[7]){ if((RX_buffer[0] == 0x00AA) && (RX_buffer[1] == 0x0010) && !Run_Flag){ display[0] = 0x00BB; for(i=1;i<7;i++) display[i] = RX_buffer[i]; display[7] = RX_buffer[7]+2; PieCtrlRegs.PIEIER9.bit.INTx4 = 1; // Send messege Run_Flag = 1; } else if((RX_buffer[0] == 0x00AA) && (RX_buffer[1] == 0x0010) && Run_Flag){ display[0] = 0x00BB; display[1] = 0x0010; display[2] = 0x00FF; // Already Running display[3] = 0x0000; display[4] = 0x0000; display[5] = 0x0000; display[6] = 0x0000; temp1 = 0; for(j=0;j<7;j++){ for(i=0;i<8;i++){ temp1 = temp1 + ((display[j]>>i)&0x01); } } display[7] = temp1; PieCtrlRegs.PIEIER9.bit.INTx4 = 1; // Send messege Run_Flag = 1; } else if((RX_buffer[0] == 0x00AA) && (RX_buffer[1] == 0x0041)){ display[0] = 0x00BB; display[1] = 0x0041; display[2] = Motor1_3NM/256; display[3] = Motor1_3NM%256; display[4] = 00; display[5] = 00; display[6] = 00; temp1 = 0; for(j=0;j<7;j++){ for(i=0;i<8;i++){ temp1 = temp1 + ((display[j]>>i)&0x01); } } display[7] = temp1; PieCtrlRegs.PIEIER9.bit.INTx4 = 1; // Send messege } else{ display = "ERROR "; PieCtrlRegs.PIEIER9.bit.INTx4 = 1; } /*for(i=0;i<8;i++) // Check received data { if(rdataB[i] != ( (rdata_pointB-i) & 0x00FF) ) error(); } rdata_pointB = (rdata_pointB-1) & 0x00FF;*/
ScibRegs.SCIFFRX.bit.RXFFOVRCLR=1; // Clear Overflow flag ScibRegs.SCIFFRX.bit.RXFFINTCLR=1; // Clear Interrupt flag PieCtrlRegs.PIEACK.all|=0x100; // Issue PIE ack LED2 = ~LED2; } else{ display = "ERROR "; PieCtrlRegs.PIEIER9.bit.INTx4 = 1; }}
void spi_ctrlio_init(void){EALLOW;
#ifdef SLAVE GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 0; GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 0; GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 0;// GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 0; GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 0; GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 0; GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 0; GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 0; GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 0; GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 0; GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 0; GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 0; GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 0; GpioCtrlRegs.GPBDIR.bit.GPIO48 = 1; GpioCtrlRegs.GPBDIR.bit.GPIO49 = 1; GpioCtrlRegs.GPBDIR.bit.GPIO50 = 1;// GpioCtrlRegs.GPBDIR.bit.GPIO51 = 1; GpioCtrlRegs.GPBDIR.bit.GPIO54 = 1; GpioCtrlRegs.GPBDIR.bit.GPIO55 = 1; GpioCtrlRegs.GPBDIR.bit.GPIO56 = 1; GpioCtrlRegs.GPBDIR.bit.GPIO57 = 1; GpioCtrlRegs.GPBDIR.bit.GPIO58 = 1; GpioCtrlRegs.GPBDIR.bit.GPIO59 = 1; GpioCtrlRegs.GPBDIR.bit.GPIO60 = 1; GpioCtrlRegs.GPBDIR.bit.GPIO61 = 1; GpioCtrlRegs.GPBDIR.bit.GPIO62 = 1; GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 0; GpioCtrlRegs.GPADIR.bit.GPIO0 = 0; GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0;
GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 0; GpioCtrlRegs.GPBDIR.bit.GPIO63 = 0; GpioCtrlRegs.GPBPUD.bit.GPIO63 = 0;
GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 0; //set the DDR pins to HZ GpioCtrlRegs.GPCDIR.bit.GPIO75 = 1;
GpioCtrlRegs.GPCMUX1.all = 0x00000000; GpioCtrlRegs.GPCMUX2.all = 0x00000000; GpioCtrlRegs.GPCDIR.all = 0x00000000; GpioCtrlRegs.GPCPUD.all = 0xFFFFFFFF;
GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 0; GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 0; GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 0; GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 0;
GpioCtrlRegs.GPBDIR.bit.GPIO45 = 0; GpioCtrlRegs.GPBDIR.bit.GPIO46 = 0; GpioCtrlRegs.GPBDIR.bit.GPIO47 = 0; GpioCtrlRegs.GPBDIR.bit.GPIO38 = 0;
GpioCtrlRegs.GPBPUD.bit.GPIO45 = 1; GpioCtrlRegs.GPBPUD.bit.GPIO46 = 1; GpioCtrlRegs.GPBPUD.bit.GPIO47 = 1; GpioCtrlRegs.GPBPUD.bit.GPIO38 = 1;#endif
/* Enable internal pull-up for the selected pins */// Pull-ups can be enabled or disabled by the user. // This will enable the pullups for the specified pins.// Comment out other unwanted lines.
//********************************This part is changed at Date 2012-10-25*********************************** GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (SPISIMOA) GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (SPISOMIA) GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up on GPIO18 (SPICLKA) GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up on GPIO19 (SPISTEA) /* GpioCtrlRegs.GPBPUD.bit.GPIO54 = 0; GpioCtrlRegs.GPBPUD.bit.GPIO55 = 0; GpioCtrlRegs.GPBPUD.bit.GPIO56 = 0; GpioCtrlRegs.GPBPUD.bit.GPIO57 = 0; GpioCtrlRegs.GPBPUD.bit.GPIO58 = 0; GpioCtrlRegs.GPBPUD.bit.GPIO59 = 0; GpioCtrlRegs.GPBPUD.bit.GPIO60 = 0; GpioCtrlRegs.GPBPUD.bit.GPIO61 = 0; */ // GpioCtrlRegs.GPBPUD.bit.GPIO54 = 0; // Enable pull-up on GPIO54 (SPISIMOA) // GpioCtrlRegs.GPBPUD.bit.GPIO55 = 0; // Enable pull-up on GPIO55 (SPISOMIA) // GpioCtrlRegs.GPBPUD.bit.GPIO56 = 0; // Enable pull-up on GPIO56 (SPICLKA) // GpioCtrlRegs.GPBPUD.bit.GPIO57 = 0; // Enable pull-up on GPIO57 (SPISTEA)
/* Set qualification for selected pins to asynch only */// This will select asynch (no qualification) for the selected pins.// Comment out other unwanted lines.
GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (SPISIMOA) GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (SPISOMIA) GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input GPIO18 (SPICLKA) GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SPISTEA)
/* GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // Asynch input GPIO16 (SPISIMOA) GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // Asynch input GPIO17 (SPISOMIA) GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // Asynch input GPIO18 (SPICLKA) GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // Asynch input GPIO19 (SPISTEA) GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // Asynch input GPIO16 (SPISIMOA) GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // Asynch input GPIO17 (SPISOMIA) GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // Asynch input GPIO18 (SPICLKA) GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // Asynch input GPIO19 (SPISTEA)*/ /* Configure SPI-A pins using GPIO regs*/// This specifies which of the possible GPIO pins will be SPI functional pins.// Comment out other unwanted lines.
GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPIO19 as SPISTEA
// GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1; // Configure GPIO54 as SPISIMOA// GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1; // Configure GPIO55 as SPISOMIA// GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1; // Configure GPIO56 as SPICLKA// GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 1; // Configure GPIO57 as SPISTEA
EDIS;}
// Modify the UART IO RXD TXDvoid InitScibGpio(void){ EALLOW; /* Enable internal pull-up for the selected pins */// Pull-ups can be enabled or disabled disabled by the user. // This will enable the pullups for the specified pins.// Comment out other unwanted lines.
// GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pull-up for GPIO9 (SCITXDB) GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pull-up for GPIO14 (SCITXDB)// GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up for GPIO18 (SCITXDB)// GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pull-up for GPIO22 (SCITXDB)
// GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pull-up for GPIO11 (SCIRXDB) GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pull-up for GPIO15 (SCIRXDB)// GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up for GPIO19 (SCIRXDB)// GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pull-up for GPIO23 (SCIRXDB)
/* Set qualification for selected pins to asynch only */// This will select asynch (no qualification) for the selected pins.// Comment out other unwanted lines.
// GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 3; // Asynch input GPIO11 (SCIRXDB) GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (SCIRXDB)// GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SCIRXDB)// GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; // Asynch input GPIO23 (SCIRXDB)
/* Configure SCI-B pins using GPIO regs*/// This specifies which of the possible GPIO pins will be SCI functional pins.// Comment out other unwanted lines.
// GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 2; // Configure GPIO9 for SCITXDB operation GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 2; // Configure GPIO14 for SCITXDB operation// GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 2; // Configure GPIO18 for SCITXDB operation// GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 3; // Configure GPIO22 for SCITXDB operation // GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 2; // Configure GPIO11 for SCIRXDB operation GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 2; // Configure GPIO15 for SCIRXDB operation// GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 2; // Configure GPIO19 for SCIRXDB operation// GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 3; // Configure GPIO23 for SCIRXDB operation EDIS;}
void adc_config(void){ // Specific ADC setup for this example: AdcRegs.ADCTRL1.bit.ACQ_PS = ADC_SHCLK; // Sequential mode: Sample rate = 1/[(2+ACQ_PS)*ADC clock in ns] // = 1/(3*40ns) =8.3MHz (for 150 MHz SYSCLKOUT) // = 1/(3*80ns) =4.17MHz (for 100 MHz SYSCLKOUT) // If Simultaneous mode enabled: Sample rate = 1/[(3+ACQ_PS)*ADC clock in ns] AdcRegs.ADCTRL3.bit.ADCCLKPS = ADC_CKPS; AdcRegs.ADCTRL1.bit.SEQ_CASC = 1; // 1 Cascaded mode // AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; AdcRegs.ADCTRL1.bit.CONT_RUN = 1; // Setup continuous run AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1; // Enable SEQ1 interrupt (every EOS) AdcRegs.ADCTRL2.bit.RST_SEQ1 = 0x1;
AdcRegs.ADCTRL1.bit.SEQ_OVRD =1; // Enable Sequencer override feature AdcRegs.ADCCHSELSEQ1.all = 0x8888; // Initialize all ADC channel selects to B0 AdcRegs.ADCCHSELSEQ2.all = 0x8888; AdcRegs.ADCCHSELSEQ3.all = 0x8888; AdcRegs.ADCCHSELSEQ4.all = 0x8888; AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0xf; // convert and store in 8 results registers}
void dma_config(void){ // Configure DMA Channel DMADest = &DMABuf1[0]; //Point DMA destination to the beginning of the array DMASource = &AdcMirror.ADCRESULT0; //Point DMA source to ADC result register base DMACH1AddrConfig(DMADest,DMASource); DMACH1BurstConfig(15,1,1); DMACH1TransferConfig(7,1,1); DMACH1WrapConfig(0xFFFF,0,0xFFFF,0); DMACH1ModeConfig(DMA_SEQ1INT,PERINT_ENABLE,ONESHOT_DISABLE,CONT_DISABLE,SYNC_DISABLE,SYNC_SRC, OVRFLOW_DISABLE,SIXTEEN_BIT,CHINT_END,CHINT_ENABLE); }
void scib_fifo_init(void){ ScibRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback // No parity,8 char bits, // async mode, idle-line protocol ScibRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK, // Disable RX ERR, SLEEP, TXWAKE ScibRegs.SCICTL2.bit.TXINTENA =1; ScibRegs.SCICTL2.bit.RXBKINTENA =1; ScibRegs.SCIHBAUD =0x0000; ScibRegs.SCILBAUD =SCI_PRD;// ScibRegs.SCICCR.bit.LOOPBKENA =1; // Enable loop back ScibRegs.SCIFFTX.all=0xC028; ScibRegs.SCIFFRX.all=0x0028; ScibRegs.SCIFFCT.all=0x00; ScibRegs.SCIFFTX.bit.SCIFFENA = 1; //WO ZIJI JIA DE ScibRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset ScibRegs.SCIFFTX.bit.TXFIFOXRESET=1; ScibRegs.SCIFFRX.bit.RXFIFORESET=1;
}
