TI中文支持网Part Number:DS90UB941AS-Q1
#1920x1080p60, Dual Link FPD III
# PCLK = 148.5MHz
# DSI clock = 445.5MHz
# DSI Lane Speed = 891Mbps/lane
# 4 Lanes DSI
# DSI input port 0
# DSI non-burst mode with sync pulses
# MODE_SEL0 strap = No. 3
# MODE_SEL1 strap = No. 0 or 1
具体寄存器：
{0x01,0x08}, //# Disable DSI
{0x40,0x04}, //# TSKIP_CNT
{0x41,0x05}, //# TSKIP_CNT
{0x42,0x30}, //# TSKIP_CNT
{0x40,0x10}, // # Init DSI Clock Settings (From Section 10.2 of datasheet)
{0x41,0x86}, //# Init DSI Clock Settings (From Section 10.2 of datasheet)
{0x42,0x0A}, // # Init DSI Clock Settings (From Section 10.2 of datasheet)
{0x41,0x94}, // # Init DSI Clock Settings (From Section 10.2 of datasheet)
{0x42,0x0A}, //# Init DSI Clock Settings (From Section 10.2 of datasheet)
{0x01,0x00}, //#Release DSI
实际读出0x5f=0x21 这样看的话 这个配置完全没有用呀 CLK都达不到
Amy Luo：
您好，
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