TI中文支持网Part Number:TMS320F28377SOther Parts Discussed in Thread:ALP, , C2000WARE
你好，我想使用CMPSS来控制PWM输出，使用TZ的方式。具体的配置代码如下：
1、PWM的配置
void sinitEPWM2_ALP(void)//GPI0_02_03
{
if (PWMorCMP == cCMPmode)
{
// EALLOW;
//// EPwm2Regs.AQSFRC.bit.RLDCSF = 3;//Action-Qualifier Software Force Load immediately
// //all pwm output low
// EPwm2Regs.AQCSFRC.all = 0x0005;
// EDIS;
EALLOW;
// Clear everything first
EPwmXbarRegs.TRIP4MUX0TO15CFG.all = 0x0000;
EPwmXbarRegs.TRIP4MUX16TO31CFG.all = 0x0000;
// Enable Muxes for ored input of CMPSS1H and 1L, i.e. .1 mux for Mux0
EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX0 = 0; //cmpss1 – tripH
// Disable all the muxes first
EPwmXbarRegs.TRIP4MUXENABLE.all = 0x0000;
// Enable Mux 0 OR Mux 4 to generate TRIP4
EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX0 = 1;
EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 3; //Trip 4 is the input to the DCAHCOMPSEL
// //EPwm2Regs.DCTRIPSEL.bit.DCALCOMPSEL = 3; //Trip 4 is the input to the DCALCOMPSEL
// EPwm2Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 3; //Trip 4 is the input to the DCBHCOMPSEL
// //EPwm2Regs.DCTRIPSEL.bit.DCBLCOMPSEL = 3; //Trip 4 is the input to the DCALCOMPSEL
// EPwm2Regs.TZDCSEL.bit.DCAEVT1 = 2;//Digital Compare Output A Event 1 Selection
//000: Event disabled
//001: DCAH = low, DCAL = don't care
//010: DCAH = high, DCAL = don't care
//011: DCAL = low, DCAH = don't care
//100: DCAL = high, DCAH = don't care
//101: DCAL = high, DCAH = low
//110: Reserved
//111: Reserved
EPwm2Regs.TZDCSEL.bit.DCAEVT2 = 2;
// EPwm2Regs.TZDCSEL.bit.DCBEVT1 = 2;
// EPwm2Regs.TZDCSEL.bit.DCBEVT2 = 2;//*************************
// EPwm2Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT1;//DCAEVT1 Source Signal Select
// //0: Source Is DCAEVT1 Signal
// //1: Source Is DCEVTFILT Signal
// EPwm2Regs.DCACTL.bit.EVT2SRCSEL = DC_EVT2;
// EPwm2Regs.DCBCTL.bit.EVT1SRCSEL = DC_EVT1;
// EPwm2Regs.DCBCTL.bit.EVT2SRCSEL = DC_EVT2;
// EPwm2Regs.DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_SYNC;//DCAEVT1 Force Synchronization Signal Select
// //0: Source is synchronized with EPWMCLK
// //1: Source is passed through asynchronously
// EPwm2Regs.DCACTL.bit.EVT2FRCSYNCSEL = DC_EVT_SYNC;
// EPwm2Regs.DCBCTL.bit.EVT1FRCSYNCSEL = DC_EVT_SYNC;
// EPwm2Regs.DCBCTL.bit.EVT2FRCSYNCSEL = DC_EVT_SYNC;
// EPwm2Regs.DCACTL.bit.EVT1SOCE = 0;
// EPwm2Regs.DCACTL.bit.EVT1SYNCE = 0;
// EPwm2Regs.DCBCTL.bit.EVT1SOCE = 0;
// EPwm2Regs.DCBCTL.bit.EVT1SYNCE = 0;
// EPwm2Regs.DCFCTL.bit.BLANKE = 1;//ENable blanking window
// EPwm2Regs.DCFCTL.bit.PULSESEL = 2;//Pulse Select For Blanking & Capture Alignment
// //00: Time-base counter equal to period (TBCTR = TBPRD)
// //01: Time-base counter equal to zero (TBCTR = 0x00)
// //10: Time-base counter equal to zero (TBCTR = 0x00) or period
// //(TBCTR = TBPRD)
// //11: Reserved
// EPwm2Regs.DCFCTL.bit.SRCSEL = 1;//Filter Block Signal Source Select
// //00: Source Is DCAEVT1 Signal
// //01: Source Is DCAEVT2 Signal
// //10: Source Is DCBEVT1 Signal
// //11: Source Is DCBEVT2 Signal
/*Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking
window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by
the DCFCTL[PULSESEL] bit. This offset register is shadowed and the active register is loaded at the reference point defined by
DCFCTL[PULSESEL]. The offset counter is also initialized and begins to count down when the active register is loaded. When the
counter expires, the blanking window is applied. If the blanking window is currently active, then the blanking window counter is
restarted.*/// EPwm2Regs.DCFOFFSET = 0;
// EPwm2Regs.DCFWINDOW = 30;
// EPwm2Regs.TZSEL.bit.CBC1 = 0;//Disable TZ1 as a CBC trip source for this ePWM module
// EPwm2Regs.TZSEL.bit.CBC2 = 0;//Disable TZ2 as a CBC trip source for this ePWM module
// EPwm2Regs.TZSEL.bit.CBC3 = 0;//Disable TZ3 as a CBC trip source for this ePWM module
// EPwm2Regs.TZSEL.bit.CBC4 = 0;//Disable TZ4 as a CBC trip source for this ePWM module
// EPwm2Regs.TZSEL.bit.CBC5 = 0;//Disable TZ5 as a CBC trip source for this ePWM module
// EPwm2Regs.TZSEL.bit.CBC6 = 0;//Disable TZ6 as a CBC trip source for this ePWM module
// EPwm2Regs.TZSEL.bit.OSHT1 = 0;//Disable TZ1 as a CBC trip source for this ePWM module
// EPwm2Regs.TZSEL.bit.OSHT2 = 0;//Disable TZ2 as a CBC trip source for this ePWM module
// EPwm2Regs.TZSEL.bit.OSHT3 = 0;//Disable TZ3 as a CBC trip source for this ePWM module
// EPwm2Regs.TZSEL.bit.OSHT4 = 0;//Disable TZ4 as a CBC trip source for this ePWM module
// EPwm2Regs.TZSEL.bit.OSHT5 = 0;//Disable TZ5 as a CBC trip source for this ePWM module
// EPwm2Regs.TZSEL.bit.OSHT6 = 0;//Disable TZ6 as a CBC trip source for this ePWM module
//// EPwm2Regs.TZSEL.bit.DCAEVT1 = 0; //Digital Compare Output A Event 1 Select
// 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module.
// 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module.
EPwm2Regs.TZSEL.bit.DCBEVT1 = 0;
EPwm2Regs.TZSEL.bit.DCAEVT2 = 1; // Digital Compare Output A Event 2 Select
//0: Disable DCAEVT2 as a CBC trip source for this ePWM module
//1: Enable DCAEVT2 as a CBC trip source for this ePWM module
//Reset type: SYSRSn
EPwm2Regs.TZSEL.bit.DCBEVT2 = 0;
EDIS;
}
//——————————————————————————–//
if (PWMorCMP == cCMPmode)
{
EPwm2Regs.TBPRD = cCMPPERIOD; // Set timer period (12.5us)500=100M/80k
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
}
else
{
// Disable all the muxes first
EPwmXbarRegs.TRIP4MUXENABLE.all = 0x0000;
EPwm2Regs.TBPRD = cPWMPERIOD; // Set timer period (12.5us)500=100M/80k/2
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
}
EPwm2Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; // Load registers every ZERO
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare
if (PWMorCMP == cCMPmode)
{
//EPwm2Regs.CMPA.bit.CMPA = 600;//if want to limit duty on comparator mode,set the value to 1250*0.95(0.99,0.98…..) //EPwm2Regs.AQCTLA2.bit.T1U = AQ_CLEAR; // if limit duty
//EPwm2Regs.AQCTLB2.bit.T1U = AQ_SET;
EPwm2Regs.AQCTLA2.bit.T1U = AQ_NO_ACTION; // if limit duty
EPwm2Regs.AQCTLB2.bit.T1U = AQ_NO_ACTION; EPwm2Regs.AQCTLA2.bit.T1D = AQ_NO_ACTION; // action disabled
EPwm2Regs.AQCTLB2.bit.T1D = AQ_NO_ACTION;
EPwm2Regs.AQCTLA2.bit.T2U = AQ_NO_ACTION; // action disabled
EPwm2Regs.AQCTLB2.bit.T2U = AQ_NO_ACTION;
EPwm2Regs.AQCTLA2.bit.T2D = AQ_NO_ACTION; // action disabled
EPwm2Regs.AQCTLB2.bit.T2D = AQ_NO_ACTION;
EPwm2Regs.AQCTLA.bit.CAU = AQ_NO_ACTION; // action disabled
EPwm2Regs.AQCTLB.bit.CAU = AQ_NO_ACTION; // EPwm2Regs.AQCTLA.bit.CAD = AQ_NO_ACTION; // action disabled
EPwm2Regs.AQCTLB.bit.CAD = AQ_NO_ACTION; //
//EPwm2Regs.AQTSRCSEL.bit.T1SEL = 1;//T1 Event Source Select Bits
//0000: DCAEVT1
//0001: DCAEVT2
//0010: DCBEVT1
//0011: DCBEVT2
//0100: TZ1
//0101: TZ2
//0110: TZ3
//0111: EPWMxSYNCI
//1xxx: Reserved
//Reset type: SYSRSn
// EPwm2Regs.AQTSRCSEL.bit.T2SEL = 3;
EPwm2Regs.AQCTLA.bit.PRD = 1;
EPwm2Regs.AQCTLA.bit.ZRO = 2;//Action When TBCTR = 0
// //Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.
// //00: Do nothing (action disabled)
// //01: Clear: force EPWMxA output low.
// //10: Set: force EPWMxA output high.
// //11: Toggle EPWMxA output: low output signal will be forced high,and a high signal will be forced low.
// //Reset type: SYSRSn
// EPwm2Regs.AQCTLB.bit.ZRO = 2;
} else
{
EPwm2Regs.CMPA.bit.CMPA = 312;
// Set actions
EPwm2Regs.AQCTLA2.bit.T1U = AQ_NO_ACTION; // if limit duty
EPwm2Regs.AQCTLB2.bit.T1U = AQ_NO_ACTION;
EPwm2Regs.AQCTLA2.bit.T1U = AQ_NO_ACTION; // if limit duty
EPwm2Regs.AQCTLB2.bit.T1U = AQ_NO_ACTION;
EPwm2Regs.AQCTLA2.bit.T1D = AQ_NO_ACTION; // action disabled
EPwm2Regs.AQCTLB2.bit.T1D = AQ_NO_ACTION;
EPwm2Regs.AQCTLA2.bit.T2U = AQ_NO_ACTION; // action disabled
EPwm2Regs.AQCTLB2.bit.T2U = AQ_NO_ACTION;
EPwm2Regs.AQCTLA2.bit.T2D = AQ_NO_ACTION; // action disabled
EPwm2Regs.AQCTLB2.bit.T2D = AQ_NO_ACTION;
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM1A on CAU
EPwm2Regs.AQCTLB.bit.CAU = AQ_NO_ACTION; // EPwm2Regs.AQCTLA.bit.CAD = AQ_SET; // Set PWM1A on CAD
EPwm2Regs.AQCTLB.bit.CAD = AQ_NO_ACTION; //
}
if (PWMorCMP == cCMPmode)
{
EALLOW;
// EPwm2Regs.TZCTL2.bit.ETZE = 0;//TZCTL2 Enable
// //0: Use trip action from TZCTL (legacy EPWM compatibility)
// //1: Use trip action defined in TZCTL2, TZCTLDCA and TZCTLDCB.
// //Settings in TZCTL are ignored
// //Reset type: SYSRSn
// EPwm2Regs.TZCTLDCA.bit.DCAEVT2U = 2;
// EPwm2Regs.TZCTLDCB.bit.DCBEVT2U = 2;
EPwm2Regs.TZCTL.bit.DCAEVT1 = 0x3; //Digital Compare Output A Event 1 Action On EPWMxA
//00: High-impedance (EPWMxA = High-impedance state)
//01: Force EPWMxA to a high state.
//10: Force EPWMxA to a low state.
//11: Do Nothing, trip action is disabled
//Reset type: SYSRSn
EPwm2Regs.TZCTL.bit.DCAEVT2 = 0x2;
EPwm2Regs.TZCTL.bit.DCBEVT1 = 0x3;
EPwm2Regs.TZCTL.bit.DCBEVT2 = 0x3;
// EPwm2Regs.TZCLR.bit.DCAEVT1 = 1;//Clear Flag for Digital Compare Output A Event 1
// //0: Writing 0 has no effect. This bit always reads back 0.
// //1: Writing 1 clears the DCAEVT1 event trip condition.
// //Reset type: SYSRSn
// EPwm2Regs.TZCLR.bit.DCAEVT2 = 1;
// EPwm2Regs.TZCLR.bit.DCBEVT1 = 1;// EPwm2Regs.TZCLR.bit.DCBEVT2 = 1;
// EPwm2Regs.TZCTL.bit.TZA = 3; //00: High-impedance (EPWMxA = High-impedance state)
// //01: Force EPWMxA to a high state
// //10: Force EPWMxA to a low state
// //11: Do nothing, no action is taken on EPWMxA.
// //Reset type: SYSRSn
//
// EPwm2Regs.TZCTL.bit.TZB = 3;
//// EPwm2Regs.TZEINT.all = 0;
// EPwm2Regs.TZCLR.bit.CBCPULSE = 0;//Clear Pulse for Cycle-By-Cycle (CBC) Trip Latch
//This bit field determines which pulse clears the CBC trip latch.
//00: CTR = zero pulse clears CBC trip latch. (Same as legacy designs.)
//01: CTR = PRD pulse clears CBC trip latch
//10: CTR = zero or CTR = PRD pulse clears CBC trip latch.
//11: CBC trip latch is not cleared
EDIS;
}
// Set Dead-Band, set to a pair PWMAB
EPwm2Regs.DBCTL.bit.IN_MODE = 0x0;
EPwm2Regs.DBCTL.bit.OUT_MODE = 0x3; //ensble DBM
EPwm2Regs.DBCTL.bit.POLSEL = 0x2;//10: Active high complementary (AHC). EPWMxB is inverted..
EPwm2Regs.DBRED.all = 50; //dead time is 0.5us=50*(1/100M)
EPwm2Regs.DBFED.all = 50; //dead time is 0.5us
// Set Trip-Zone
EALLOW;
EPwm2Regs.TZCTL.bit.TZA = 0x2; //0-High impedance;1-force to high state;2-force to low state;3-no change
EPwm2Regs.TZCTL.bit.TZB = 0x2;
// EPwm2Regs.TZCTL.bit.DCAEVT1 = 0x3;//Do Nothing, trip action is disabled
// EPwm2Regs.TZCTL.bit.DCAEVT2 = 0x3;//Do Nothing, trip action is disabled
// EPwm2Regs.TZCTL.bit.DCBEVT1 = 0x3;
// EPwm2Regs.TZCTL.bit.DCBEVT2 = 0x3;
EPwm2Regs.TZFRC.bit.OST = 0x1;
EDIS;
}
2.CMPSS的配置
void sInitCMPSS1(void)
{
EALLOW;
//
//Enable CMPSS
//
Cmpss1Regs.COMPCTL.bit.COMPDACE = 1;
//
//NEG signal comes from DAC
//
Cmpss1Regs.COMPCTL.bit.COMPHSOURCE = 0;
Cmpss1Regs.COMPCTL.bit.COMPLSOURCE = 0;
// COMP-H-L output is NOT inverted
Cmpss1Regs.COMPCTL.bit.COMPHINV = 0;
Cmpss1Regs.COMPCTL.bit.COMPLINV = 0;
//Disable aynch COMP-H-L ouput
Cmpss1Regs.COMPCTL.bit.ASYNCHEN = 0;
Cmpss1Regs.COMPCTL.bit.ASYNCLEN = 0;
// Configure CTRIPOUT path
// Digital filter output feeds CTRIPH and CTRIPOUTH
//
// High comparator CTRIPH source select.
//0 Asynchronous comparator output drives CTRIPH
//1 Synchronous comparator output drives CTRIPH
// 2 Output of digital filter drives CTRIPH
//3 Latched output of digital filter drives CTRIPH
Cmpss1Regs.COMPCTL.bit.CTRIPHSEL = 1;
Cmpss1Regs.COMPCTL.bit.CTRIPLSEL = 1;
Cmpss1Regs.COMPCTL.bit.CTRIPOUTHSEL = 1;
Cmpss1Regs.COMPCTL.bit.CTRIPOUTLSEL = 1;
// Set up COMPHYSCTL register
Cmpss1Regs.COMPHYSCTL.bit.COMPHYS = 0; //Comparator hysteresis. Sets the amount of hysteresis on the comparator inputs.
//0 None
//1 Set to typical hysteresis,12
//2 Set to 2x of typical hysteresis,24
//3 Set to 3x of typical hysteresis,36
//4 Set to 4x of typical hysteresis,48
//Use VDDA as the reference for DAC
Cmpss1Regs.COMPDACCTL.bit.SELREF = 0;
Cmpss1Regs.COMPDACCTL.bit.SWLOADSEL = 1; //Software load select. Determines whether DACxVALA is updated
//from DACxVALS on SYSCLK or EPWMSYNCPER.
//0 DACxVALA is updated from DACxVALS on SYSCLK
//1 DACxVALA is updated from DACxVALS on EPWMSYNCPER
//Reset type: SYSRSn
Cmpss1Regs.COMPDACCTL.bit.DACSOURCE = 0; // Ramp bypassed ,Ramp generator source select. Determines which EPWMSYNCPER,EPWM2SYNCPER
// Load DACs – High and Low
Cmpss1Regs.DACHVALS.bit.DACVAL = 300;
Cmpss1Regs.DACLVALS.bit.DACVAL = 300;
//
// Configure Digital Filter
//Maximum CLKPRESCALE value provides the most time between samples,1MHZ
//
Cmpss1Regs.CTRIPHFILCLKCTL.bit.CLKPRESCALE = 0xC7;//samples = SAMPWIN + 1, threshold = THRESH + 1
//and prescale =CLKPRESCALE + 1.
Cmpss1Regs.CTRIPLFILCLKCTL.bit.CLKPRESCALE = 0xC7;
//
//Maximum SAMPWIN value provides largest number of samples
//
Cmpss1Regs.CTRIPHFILCTL.bit.SAMPWIN = 0x1F;
Cmpss1Regs.CTRIPLFILCTL.bit.SAMPWIN = 0x1F;
//
//Maximum THRESH value requires static value for entire window
// THRESH should be GREATER than half of SAMPWIN
//
Cmpss1Regs.CTRIPHFILCTL.bit.THRESH = 0x1F;
Cmpss1Regs.CTRIPLFILCTL.bit.THRESH = 0x1F;
//
//Reset filter logic & start filtering,Initialize all samples to the filter input value
//
Cmpss1Regs.CTRIPHFILCTL.bit.FILINIT = 1;
Cmpss1Regs.CTRIPLFILCTL.bit.FILINIT = 1;
//
// Clear the status register for latched comparator events
Cmpss1Regs.COMPSTSCLR.bit.HLATCHCLR = 1;
Cmpss1Regs.COMPSTSCLR.bit.LLATCHCLR = 1;
// Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch
Cmpss1Regs.COMPSTSCLR.bit.HSYNCCLREN = 1;
Cmpss1Regs.COMPSTSCLR.bit.LSYNCCLREN = 1;
// Configure CTRIPOUTH output pin
// Configure OUTPUTXBAR1 to be CTRIPOUT1H
//
OutputXbarRegs.OUTPUT1MUX0TO15CFG.bit.MUX0 = 1;
//
//Enable OUTPUTXBAR1 Mux for Output
//
OutputXbarRegs.OUTPUT1MUXENABLE.bit.MUX0 = 1;
EDIS;
}
得到的波形如下：
其中黄色是CTRIPOUT1H信号，绿色是EPWM2A的信号，EPWM2A与EPWM2B设置为互补模式。本意是想让只要CTRIPOUT1H为高的时候（产生DCAEVT2 ），PWM就要通过TZ的方式关断PWM，但实际测试的波形是一直没有关断。为了让波形更加明显，一直让CTRIPOUT1H为高（不是上面的方波），测试的波形如下：
就是说产生的DCAEVT2一直没有让PWM模块的TZ功能生效，请问是什么原因？
Green Deng：
你好，按照下面的设置再试一下：
EPwm2Regs.TZDCSEL.bit.DCAEVT2 = TZ_DCAH_HI; EPwm2Regs.DCACTL.bit.EVT2SRCSEL = DC_EVT2; //... EPwm2Regs.TZSEL.bit.DCAEVT2 = 1; //... EPwm2Regs.TZCTL.bit.DCAEVT2 = TZ_FORCE_LO;
,
user1078330：
请问你们关于TMS320F28377S有没有关于CMPSS与PWM联合使用的例程？我发现好多人都在问这个问题
,
Green Deng：
你可以在这个路径找到库形式的例程：C:\ti\c2000\C2000Ware_3_04_00_00\driverlib\f2837xs\examples\cpu1\epwm
寄存器版的目前还没有
,
user1078330：
我发现只有把EPwm2Regs.TZCTL2.bit.ETZE = 1，才可以使EPwm2Regs.TZCTL.bit.DCAEVT2 = TZ_FORCE_LO生效，但是数据手册中不是这么说的，请问这是什么原因？
,
Green Deng：
额，按照手册说明，ETZE置1的话是会忽视TZCTL的动作设置。所以你这边测到的是跟手册说明的相反？
