TMS320F280049: 关于中断的使能

epwm.txt

#include "f28004x_device.h"// Header File Include File
#include <Drv_config.h>// Examples Include File

//---------------------------------------------------------------------------
// InitEPwm: 
//---------------------------------------------------------------------------
// This function initializes the ePWM(s) to a known state.
//
void InitEPwm(void)
{
	// Initialize ePWM
	InitEPwm1Gpio();
	InitEPwm2Gpio();
	InitEPwm3Gpio();
	InitEPwm4Gpio();
	InitEPwm5Gpio();
	InitEPwm6Gpio();
	InitEPwmFAN();
	
	InitTz();//
	
	//mOffDcdcPwm();
	InitEPwm1();
	InitEPwm2();
	InitEPwm3();
	InitEPwm4();
	InitEPwm5();
	InitEPwm6();

	InitEPwm7();//Trigger ADCSOC
	InitEPwm8();//FAN PWM

	EALLOW;EPwm1Regs.TBCTL.bit.SWFSYNC = 1; //���ͬ��һ��DC�ĸ�PWM���ع�,1Ϊmaster
	EDIS;
}

void InitEPwm1Gpio(void)
{EALLOW;

/* Disable or Enable internal pull-up for the selected output pins for reduced power consumption */
// Pull-ups can be enabled or disabled by the user.
// Comment out other unwanted lines.//GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0;// Enable pullup on GPIO0//GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0;// Enable pullup on GPIO1GpioCtrlRegs.GPAPUD.bit.GPIO0 = 1;// Disable pull-up on GPIO0 (EPWM1A)GpioCtrlRegs.GPAPUD.bit.GPIO1 = 1;// Disable pull-up on GPIO1 (EPWM1B)

/* Configure EPWM-1 pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be EPWM1 functional pins.
// Comment out other unwanted lines.GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1;// Configure GPIO0 as EPWM1AGpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1;// Configure GPIO1 as EPWM1BEDIS;
}

void InitEPwm2Gpio(void)
{EALLOW;

/* Disable or Enable internal pull-up for the selected output pinsfor reduced power consumption */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.//GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0;// Enable pullup on GPIO2//GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0;// Enable pullup on GPIO3GpioCtrlRegs.GPAPUD.bit.GPIO2 = 1;// Disable pull-up on GPIO2 (EPWM2A)GpioCtrlRegs.GPAPUD.bit.GPIO3 = 1;// Disable pull-up on GPIO3 (EPWM2B)

/* Configure EPwm-2 pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be EPWM2 functional pins.
// Comment out other unwanted lines.GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1;// Configure GPIO2 as EPWM2AGpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1;// Configure GPIO3 as  EPWM2BEDIS;
}

void InitEPwm3Gpio(void)
{EALLOW;

/* Disable or Enable internal pull-up for the selected output pinsfor reduced power consumption */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.//GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0;// Enable pullup on GPIO4//GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0;// Enable pullup on GPIO5GpioCtrlRegs.GPAPUD.bit.GPIO4 = 1;// Disable pull-up on GPIO4 (EPWM3A)GpioCtrlRegs.GPAPUD.bit.GPIO5 = 1;// Disable pull-up on GPIO5 (EPWM3B)

/* Configure EPwm-3 pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be EPWM3 functional pins.
// Comment out other unwanted lines.GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1;// Configure GPIO4 as EPWM3AGpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1;// Configure GPIO5 as EPWM3BEDIS;
}

void InitEPwm4Gpio(void)
{EALLOW;
/* Disable or Enable internal pull-up for the selected output pinsfor reduced power consumption */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.//GpioCtrlRegs.GPAPUD.bit.GPIO6 = 1;// Enable pull-up on GPIO6 (EPWM4A)//GpioCtrlRegs.GPAPUD.bit.GPIO7 = 1;// Enable pull-up on GPIO7 (EPWM4B)GpioCtrlRegs.GPAPUD.bit.GPIO6 = 1;// Disable pull-up on GPIO6 (EPWM4A)GpioCtrlRegs.GPAPUD.bit.GPIO7 = 1;// Disable pull-up on GPIO7 (EPWM4B)

/* Configure EPWM-4 pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be EPWM4 functional pins.
// Comment out other unwanted lines.GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1;// Configure GPIO6 as EPWM4AGpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1;// Configure GPIO7 as EPWM4BEDIS;
}

void InitEPwm5Gpio(void)
{EALLOW;
/* Disable or Enable internal pull-up for the selected output pins for reduced power consumption */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.//GpioCtrlRegs.GPAPUD.bit.GPIO8 = 1;// Enable pull-up on GPIO8 (EPWM5A)//GpioCtrlRegs.GPAPUD.bit.GPIO9 = 1;// Enable pull-up on GPIO9 (EPWM5B)GpioCtrlRegs.GPAPUD.bit.GPIO8 = 1;// Disable pull-up on GPIO8 (EPWM5A)GpioCtrlRegs.GPAPUD.bit.GPIO9 = 1;// Disable pull-up on GPIO9 (EPWM5B)

/* Configure EPWM-5 pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be EPWM5 functional pins.
// Comment out other unwanted lines.GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1;// Configure GPIO8 as EPWM5A,not GPIOGpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1;// Configure GPIO9 as EPWM5B,not GPIOEDIS;
}

void InitEPwm6Gpio(void)
{EALLOW;
/* Disable or Enable internal pull-up for the selected output pins for reduced power consumption */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.//GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0;// Disable pull-up on GPIO10 (EPWM6A)//GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0;// Disable pull-up on GPIO11 (EPWM6B)GpioCtrlRegs.GPAPUD.bit.GPIO10 = 1;// Disable pull-up on GPIO10 (EPWM6A)GpioCtrlRegs.GPAPUD.bit.GPIO11 = 1;// Disable pull-up on GPIO11 (EPWM6B)

/* Configure EPWM-6 pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be EPWM6 functional pins.
// Comment out other unwanted lines.GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1;// Configure GPIO10 as GPIO,not EPWM6AGpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1;// Configure GPIO11 as GPIO,not EPWM6BEDIS;
}

void InitEPwmFAN(void)
{EALLOW;
/* Disable or Enable internal pull-up for the selected output pins for reduced power consumption */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.//GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0;// Disable pull-up on GPIO10 (EPWM6A)//GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0;// Disable pull-up on GPIO11 (EPWM6B)//GpioCtrlRegs.GPAPUD.bit.GPIO10 = 1;// Disable pull-up on GPIO10 (EPWM6A)GpioCtrlRegs.GPAPUD.bit.GPIO15 = 1;// Disable pull-up on GPIO11 (EPWM6B)

/* Configure EPWM-6 pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be EPWM6 functional pins.
// Comment out other unwanted lines.//GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1;// Configure GPIO10 as GPIO,not EPWM6AGpioCtrlRegs.GPAMUX1.bit.GPIO15 = 1;// Configure GPIO11 as GPIO,not EPWM6BEDIS;
}


void InitTz()
{
	//EPwm1
	EALLOW;
	EPwm1Regs.TZCLR.bit.CBC = 1;		//Clear trip
	EPwm1Regs.TZSEL.bit.CBC1 = 1;//CBC
	EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO;///TZ_FORCE_LO;
	EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO;EPwm1Regs.TZDCSEL.bit.DCBEVT2 =0x2;//DCBH = high, DCBL = don't care//001: DCBH = low, DCBL = don't care//010: DCBH = high, DCBL = don't care//011: DCBL = low, DCBH = don't care//100: DCBL = high, DCBH = don't care//101: DCBL = high, DCBH = lowEPwm1Regs.DCBHTRIPSEL.bit.TRIPINPUT4 = 1;//ѡ����բ����4��ΪDCBH mux����ϡ�������EPwm1Regs.DCBHTRIPSEL.bit.TRIPINPUT5 = 1;EPwm1Regs.DCBHTRIPSEL.bit.TRIPINPUT7 = 1;EPwm1Regs.DCBHTRIPSEL.bit.TRIPINPUT8 = 1;EPwm1Regs.DCBHTRIPSEL.bit.TRIPINPUT9 = 1;EPwm1Regs.DCBHTRIPSEL.bit.TRIPINPUT10 = 1;EPwm1Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 0xf;//TZ����������Ȩ����EPwm1Regs.TZSEL.bit.DCBEVT2 =0x01;//�Ƚ������B CBC trip sourceEPwm1Regs.DCBCTL.bit.EVT2SRCSEL = 0;
	EDIS;

	//EPwm2
	EALLOW;
	EPwm2Regs.TZCLR.bit.CBC = 1;//Clear tripEPwm2Regs.TZSEL.bit.CBC1 = 1;//CBCEPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO;///TZ_FORCE_LO;EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO;EPwm2Regs.TZDCSEL.bit.DCBEVT2 =0x2;//DCBH = high, DCBL = don't care//001: DCBH = low, DCBL = don't care//010: DCBH = high, DCBL = don't care//011: DCBL = low, DCBH = don't care//100: DCBL = high, DCBH = don't care//101: DCBL = high, DCBH = lowEPwm2Regs.DCBHTRIPSEL.bit.TRIPINPUT4 = 1;//ѡ����բ����4��ΪDCBH mux����ϡ�������EPwm2Regs.DCBHTRIPSEL.bit.TRIPINPUT5 = 1;EPwm2Regs.DCBHTRIPSEL.bit.TRIPINPUT7 = 1;EPwm2Regs.DCBHTRIPSEL.bit.TRIPINPUT8 = 1;EPwm2Regs.DCBHTRIPSEL.bit.TRIPINPUT9 = 1;EPwm2Regs.DCBHTRIPSEL.bit.TRIPINPUT10 = 1;EPwm2Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 0xf;//TZ����������Ȩ����EPwm2Regs.TZSEL.bit.DCBEVT2 =0x01;//�Ƚ������B CBC trip sourceEPwm2Regs.DCBCTL.bit.EVT2SRCSEL = 0;
	EDIS;

	//EPwm3
	EALLOW;EPwm3Regs.TZCLR.bit.CBC = 1;//Clear tripEPwm3Regs.TZSEL.bit.CBC1 = 1;//CBCEPwm3Regs.TZCTL.bit.TZA = TZ_FORCE_LO;///TZ_FORCE_LO;EPwm3Regs.TZCTL.bit.TZB = TZ_FORCE_LO;EPwm3Regs.TZDCSEL.bit.DCBEVT2 =0x2;//DCBH = high, DCBL = don't care//001: DCBH = low, DCBL = don't care//010: DCBH = high, DCBL = don't care//011: DCBL = low, DCBH = don't care//100: DCBL = high, DCBH = don't care//101: DCBL = high, DCBH = lowEPwm3Regs.DCBHTRIPSEL.bit.TRIPINPUT4 = 1;//ѡ����բ����4��ΪDCBH mux����ϡ�������EPwm3Regs.DCBHTRIPSEL.bit.TRIPINPUT5 = 1;EPwm3Regs.DCBHTRIPSEL.bit.TRIPINPUT7 = 1;EPwm3Regs.DCBHTRIPSEL.bit.TRIPINPUT8 = 1;EPwm3Regs.DCBHTRIPSEL.bit.TRIPINPUT9 = 1;EPwm3Regs.DCBHTRIPSEL.bit.TRIPINPUT10 = 1;EPwm3Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 0xf;//TZ����������Ȩ����EPwm3Regs.TZSEL.bit.DCBEVT2 =0x01;//�Ƚ������B CBC trip sourceEPwm3Regs.DCBCTL.bit.EVT2SRCSEL = 0;
	EDIS;

	//EPwm4
	EALLOW;EPwm4Regs.TZCLR.bit.CBC = 1;//Clear tripEPwm4Regs.TZSEL.bit.CBC1 = 1;//CBCEPwm4Regs.TZCTL.bit.TZA = TZ_FORCE_LO;///TZ_FORCE_LO;EPwm4Regs.TZCTL.bit.TZB = TZ_FORCE_LO;EPwm4Regs.TZDCSEL.bit.DCBEVT2 =0x2;//DCBH = high, DCBL = don't care//001: DCBH = low, DCBL = don't care//010: DCBH = high, DCBL = don't care//011: DCBL = low, DCBH = don't care//100: DCBL = high, DCBH = don't care//101: DCBL = high, DCBH = lowEPwm4Regs.DCBHTRIPSEL.bit.TRIPINPUT4 = 1;//ѡ����բ����4��ΪDCBH mux����ϡ�������EPwm4Regs.DCBHTRIPSEL.bit.TRIPINPUT5 = 1;EPwm4Regs.DCBHTRIPSEL.bit.TRIPINPUT7 = 1;EPwm4Regs.DCBHTRIPSEL.bit.TRIPINPUT8 = 1;EPwm4Regs.DCBHTRIPSEL.bit.TRIPINPUT9 = 1;EPwm4Regs.DCBHTRIPSEL.bit.TRIPINPUT10 = 1;EPwm4Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 0xf;//TZ����������Ȩ����EPwm4Regs.TZSEL.bit.DCBEVT2 =0x01;//�Ƚ������B CBC trip sourceEPwm4Regs.DCBCTL.bit.EVT2SRCSEL = 0;
	EDIS;

	//EPwm5EALLOW;EPwm5Regs.TZCLR.bit.CBC = 1;//Clear tripEPwm5Regs.TZSEL.bit.CBC1 = 1;//CBCEPwm5Regs.TZCTL.bit.TZA = TZ_FORCE_LO;///TZ_FORCE_LO;EPwm5Regs.TZCTL.bit.TZB = TZ_FORCE_LO;EPwm5Regs.TZDCSEL.bit.DCBEVT2 =0x2;//DCBH = high, DCBL = don't care//001: DCBH = low, DCBL = don't care//010: DCBH = high, DCBL = don't care//011: DCBL = low, DCBH = don't care//100: DCBL = high, DCBH = don't care//101: DCBL = high, DCBH = lowEPwm5Regs.DCBHTRIPSEL.bit.TRIPINPUT4 = 1;//ѡ����բ����4��ΪDCBH mux����ϡ�������EPwm5Regs.DCBHTRIPSEL.bit.TRIPINPUT5 = 1;EPwm5Regs.DCBHTRIPSEL.bit.TRIPINPUT7 = 1;EPwm5Regs.DCBHTRIPSEL.bit.TRIPINPUT8 = 1;EPwm5Regs.DCBHTRIPSEL.bit.TRIPINPUT9 = 1;EPwm5Regs.DCBHTRIPSEL.bit.TRIPINPUT10 = 1;EPwm5Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 0xf;//TZ����������Ȩ����EPwm5Regs.TZSEL.bit.DCBEVT2 =0x01;//�Ƚ������B CBC trip sourceEPwm5Regs.DCBCTL.bit.EVT2SRCSEL = 0;EDIS;//EPwm6EALLOW;EPwm6Regs.TZCLR.bit.CBC = 1;//Clear tripEPwm6Regs.TZSEL.bit.CBC1 = 1;//CBCEPwm6Regs.TZCTL.bit.TZA = TZ_FORCE_LO;///TZ_FORCE_LO;EPwm6Regs.TZCTL.bit.TZB = TZ_FORCE_LO;EPwm6Regs.TZDCSEL.bit.DCBEVT2 =0x2;//DCBH = high, DCBL = don't care//001: DCBH = low, DCBL = don't care//010: DCBH = high, DCBL = don't care//011: DCBL = low, DCBH = don't care//100: DCBL = high, DCBH = don't care//101: DCBL = high, DCBH = lowEPwm6Regs.DCBHTRIPSEL.bit.TRIPINPUT4 = 1;//ѡ����բ����4��ΪDCBH mux����ϡ�������EPwm6Regs.DCBHTRIPSEL.bit.TRIPINPUT5 = 1;EPwm6Regs.DCBHTRIPSEL.bit.TRIPINPUT7 = 1;EPwm6Regs.DCBHTRIPSEL.bit.TRIPINPUT8 = 1;EPwm6Regs.DCBHTRIPSEL.bit.TRIPINPUT9 = 1;EPwm6Regs.DCBHTRIPSEL.bit.TRIPINPUT10 = 1;EPwm6Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 0xf;//TZ����������Ȩ����EPwm6Regs.TZSEL.bit.DCBEVT2 =0x01;//�Ƚ������B CBC trip sourceEPwm6Regs.DCBCTL.bit.EVT2SRCSEL = 0;EDIS;

	InitTzXbar();
}

void InitTzXbar(void)
{EALLOW;EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX2 =0x0;// 00 : Select .0 input for Mux0EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX2 =0x1;//Mux0����Ӧ���������������;EPwmXbarRegs.TRIP5MUX0TO15CFG.bit.MUX3 =0x0;// 00 : Select .0 input for Mux0EPwmXbarRegs.TRIP5MUXENABLE.bit.MUX3 =0x1;//Mux0����Ӧ���������������;EPwmXbarRegs.TRIP7MUX0TO15CFG.bit.MUX6 = 0x0;EPwmXbarRegs.TRIP7MUXENABLE.bit.MUX6 = 0x1;EPwmXbarRegs.TRIP8MUX0TO15CFG.bit.MUX7 = 0x0;EPwmXbarRegs.TRIP8MUXENABLE.bit.MUX7 = 0x1;EPwmXbarRegs.TRIP9MUX0TO15CFG.bit.MUX8 = 0x0;EPwmXbarRegs.TRIP9MUXENABLE.bit.MUX8 = 0x1;EPwmXbarRegs.TRIP10MUX0TO15CFG.bit.MUX9 = 0x0;EPwmXbarRegs.TRIP10MUXENABLE.bit.MUX9 = 0x1;EDIS;

}

void InitEPwm1(void)
{
// ePWM channel register configuration with HRPWM
// ePWMxA toggle low/high with MEP control on Rising edgeEALLOW;CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;// Disable TBCLK within the EPWMEDIS;///EPWM2 config config for PWM2A/2BEPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;// set Shadow loadEPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD;// (60M/250k-1)=239 Set timer period-120kHz,PWM frequency = 1/(2*TBPRD)EPwm1Regs.CMPA.bit.CMPA = EPWM1_MIN_CMPA;EPwm1Regs.CMPA.bit.CMPAHR = 0;// initialize HRPWM extensionEPwm1Regs.CMPB.bit.CMPB = EPWM1_TIMER_TBPRD - EPWM1_MIN_CMPA;EPwm1Regs.CMPB.bit.CMPBHR = 0;EPwm1Regs.TBPHS.all = 0;EPwm1Regs.TBCTR = 0;// Setup TBCLKEPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;//TB_COUNT_UPDOWN TB_COUNT_UP;	// Select up-down count modeEPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE;	// TB_ENABLE TB_DISABLE: TBCTR phase load on SYNC (required for updown count HR controlEPwm1Regs.TBCTL.bit.PHSDIR = TB_UP; 				// Count TB_UP on syncEPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;		// pass onEPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;	// Clock ratio to SYSCLKOUTEPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;	// TBCLK = SYSCLKOUT / (HSPCLKDIV CLKDIV)EPwm1Regs.TBCTL.bit.FREE_SOFT = 11;//TBPRD is loaded from its shadow register on Counter = 0 event (CTR_zero)EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;//CC_CTR_ZERO_PRD;EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;//CC_CTR_ZERO_PRD;EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;//���������ظ߾���Ϊ�½��ظ߾���EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;	//���������ظ߾���Ϊ�½��ظ߾���EPwm1Regs.AQCTLB.bit.CBD = AQ_CLEAR;EPwm1Regs.AQCTLB.bit.CBU = AQ_SET;
///EPwm1Regs.AQSFRC.bit.RLDCSF = 3;		//AQCSFRC Active Register Reload immediately//Setup DeadbandEPwm1Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;///DBB_ENABLE;//S1=1,S0=0
///EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HI;//S3=0,S2=0
///EPwm1Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED;//S5=1,S4=0
///EPwm1Regs.DBRED = DC_DB_TIME_300NS;//DC_DB_TIME_300NS;// Interrupt where we will change the DeadbandEPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;		// Select INT on Zero & PRD eventEPwm1Regs.ETSEL.bit.INTEN = 1;					// Disable INTEPwm1Regs.ETPS.bit.INTPRD = ET_1ST;				// Generate INT on 1st event

//EALLOW;
//EPwm1Regs.HRCNFG.all = 0x0;
//EPwm1Regs.HRCNFG.bit.HRLOAD  = HR_CTR_ZERO_PRD; 		//HR_CTR_ZERO_PRD load COMPAHR on CTR = 0 and CTR = TBPRD;HR_CTR_ZERO_PRD
//EPwm1Regs.HRCNFG.bit.AUTOCONV = 1;	// Enable autoconversion for HR period
//EPwm1Regs.HRCNFG.bit.EDGMODE = HR_BEP;	// MEP control on both edges
//EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP;	// CMPAHR and TBPRDHR HR control
//
//EPwm1Regs.HRPCTL.bit.TBPHSHRLOADE = 1;	// Enable TBPHSHR sync (required for updwn count HR control)
//EPwm1Regs.HRPCTL.bit.HRPE = 1;	// Turn on high-resolution period control.
//
/////SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;// Enable TBCLK within the EPWM
/////EPwm1Regs.TBCTL.bit.SWFSYNC = 1;	// Synchronize high resolution phase to start HR period
//EDIS;

}

void InitEPwm2(void)
{

// ePWM channel register configuration with HRPWM
// ePWMxA toggle low/high with MEP control on Rising edgeEALLOW;CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;// Disable TBCLK within the EPWMEDIS;///EPWM2 config config for PWM2A/2BEPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;// set Shadow loadEPwm2Regs.TBPRD = EPWM1_TIMER_TBPRD;// (60M/250k-1)=239 Set timer period-120kHz,PWM frequency = 1/(2*TBPRD)EPwm2Regs.CMPA.bit.CMPA = EPWM1_MIN_CMPA;EPwm2Regs.CMPA.bit.CMPAHR = 0;// initialize HRPWM extensionEPwm2Regs.CMPB.bit.CMPB = EPWM1_TIMER_TBPRD - EPWM1_MIN_CMPA;EPwm2Regs.CMPB.bit.CMPBHR = 0;EPwm2Regs.TBPHS.all = 0;EPwm2Regs.TBCTR = 0;// Setup TBCLKEPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;//TB_COUNT_UPDOWN TB_COUNT_UP;	// Select up-down count modeEPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;	// TB_ENABLE TB_DISABLE: TBCTR phase load on SYNC (required for updown count HR controlEPwm2Regs.TBCTL.bit.PHSDIR = TB_UP; 				// Count TB_UP on syncEPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;		// Pass onEPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;	// Clock ratio to SYSCLKOUTEPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;	// TBCLK = SYSCLKOUT / (HSPCLKDIV CLKDIV)EPwm2Regs.TBCTL.bit.FREE_SOFT = 11;EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;// Set actionsEPwm2Regs.AQCTLA.bit.CAD = AQ_SET;EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;EPwm2Regs.AQCTLB.bit.CBD = AQ_CLEAR;EPwm2Regs.AQCTLB.bit.CBU = AQ_SET;

///EPwm2Regs.AQSFRC.bit.RLDCSF = 3;		//AQCSFRC Active Register Reload immediately// Active Low PWMs - Setup DeadbandEPwm2Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;///DBB_ENABLE;//S1=1,S0=0
//EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HI;//S3=0,S2=0
//EPwm2Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED;//S5=1,S4=0
//EPwm2Regs.DBRED = DC_DB_TIME_300NS;// Interrupt where we will change the DeadbandEPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_PRD;			// Select INT on Zero eventEPwm2Regs.ETSEL.bit.INTEN = 0;					// Disable INTEPwm2Regs.ETPS.bit.INTPRD = ET_1ST;				// Generate INT on 1st event

//EALLOW;
//EPwm2Regs.HRCNFG.all = 0x0;
//EPwm2Regs.HRCNFG.bit.HRLOAD  = HR_CTR_ZERO_PRD; 		// load on CTR = 0 and CTR = TBPRD
//EPwm2Regs.HRCNFG.bit.AUTOCONV = 1;	// Enable autoconversion for HR period
//EPwm2Regs.HRCNFG.bit.EDGMODE = HR_BEP;	// MEP control on both edges
//EPwm2Regs.HRCNFG.bit.CTLMODE = HR_CMP;	// CMPAHR and TBPRDHR HR control
//
//EPwm2Regs.HRPCTL.bit.TBPHSHRLOADE = 1;	// Enable TBPHSHR sync (required for updwn count HR control)
//EPwm2Regs.HRPCTL.bit.HRPE = 1;	// Turn on high-resolution period control.
//
/////EPwm2Regs.TBCTL.bit.SWFSYNC = 1;	// Synchronize high resolution phase to start HR period
////SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;// Enable TBCLK within the EPWM
//EDIS;
}

void InitEPwm3(void)
{
// ePWM channel register configuration with HRPWM
// ePWMxA toggle low/high with MEP control on Rising edgeEALLOW;CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;// Disable TBCLK within the EPWMEDIS;///EPWM3 config config for PWM2A/2BEPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;// set Shadow loadEPwm3Regs.TBPRD = EPWM1_TIMER_TBPRD;// (60M/250k-1)=239 Set timer period-120kHz,PWM frequency = 1/(2*TBPRD)EPwm3Regs.CMPA.bit.CMPA = EPWM1_MIN_CMPA;EPwm3Regs.CMPA.bit.CMPAHR = 0;// initialize HRPWM extensionEPwm3Regs.CMPB.bit.CMPB = EPWM1_TIMER_TBPRD - EPWM1_MIN_CMPA;EPwm3Regs.CMPB.bit.CMPBHR = 0;EPwm3Regs.TBPHS.all = 0;EPwm3Regs.TBCTR = 0;// Setup TBCLKEPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;	// Select up-down count modeEPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;	//TB_ENABLE: TBCTR phase load on SYNC (required for updown count HR controlEPwm3Regs.TBCTL.bit.PHSDIR = TB_UP; 				// Count TB_UP on sync (=120 deg)EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;		// TB_SYNC_DISABLE TB_SYNC_INEPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;	// Clock ratio to SYSCLKOUTEPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;	// TBCLK = SYSCLKOUT / (HSPCLKDIV CLKDIV)EPwm3Regs.TBCTL.bit.FREE_SOFT = 11;EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;// Set actionsEPwm3Regs.AQCTLA.bit.CAD = AQ_SET;EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR;EPwm3Regs.AQCTLB.bit.CBD = AQ_CLEAR;EPwm3Regs.AQCTLB.bit.CBU = AQ_SET;
///EPwm3Regs.AQSFRC.bit.RLDCSF = 3;		//AQCSFRC Active Register Reload immediately// Active Low PWMs - Setup DeadbandEPwm3Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;///DBB_ENABLE;//S1=1,S0=0
///EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HI;//S3=0,S2=0
///EPwm3Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED;//S5=1,S4=0
///EPwm3Regs.DBRED = DC_DB_TIME_300NS;// Interrupt where we will change the DeadbandEPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_PRD;			// Select INT on Prd eventEPwm3Regs.ETSEL.bit.INTEN = 0;					// Disable INTEPwm3Regs.ETPS.bit.INTPRD = ET_1ST;				// Generate INT on 1st event
//EALLOW;
//EPwm3Regs.HRCNFG.all = 0x0;
//EPwm3Regs.HRCNFG.bit.HRLOAD  = HR_CTR_ZERO_PRD; 		// load on CTR = 0 and CTR = TBPRD
//EPwm3Regs.HRCNFG.bit.AUTOCONV = 1;	// Enable autoconversion for HR period
//EPwm3Regs.HRCNFG.bit.EDGMODE = HR_FEP;///HR_BEP;	// MEP control on both edges
//EPwm3Regs.HRCNFG.bit.CTLMODE = HR_CMP;	// CMPAHR and TBPRDHR HR control
//
//EPwm3Regs.HRPCTL.bit.TBPHSHRLOADE = 1;	// Enable TBPHSHR sync (required for updwn count HR control)
//EPwm3Regs.HRPCTL.bit.HRPE = 1;	// Turn on high-resolution period control.
//
////EPwm3Regs.TBCTL.bit.SWFSYNC = 1;	// Synchronize high resolution phase to start HR period
////SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;// Enable TBCLK within the EPWM
//EDIS;
}

void InitEPwm4(void)
{
// ePWM channel register configuration with HRPWM
// ePWMxA toggle low/high with MEP control on Rising edgeEALLOW;CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;// Disable TBCLK within the EPWMEDIS;///EPWM4 config config for PWM2A/2BEPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;// set Shadow loadEPwm4Regs.TBPRD = EPWM1_TIMER_TBPRD;// (60M/250k-1)=239 Set timer period-120kHz,PWM frequency = 1/(2*TBPRD)EPwm4Regs.CMPA.bit.CMPA = EPWM1_MIN_CMPA;EPwm4Regs.CMPA.bit.CMPAHR = 0;// initialize HRPWM extensionEPwm4Regs.CMPB.bit.CMPB = EPWM1_TIMER_TBPRD - EPWM1_MIN_CMPA;EPwm4Regs.CMPB.bit.CMPBHR = 0;EPwm4Regs.TBPHS.all = 0;EPwm4Regs.TBCTR = 0;// Setup TBCLKEPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;	// Select up-down count modeEPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE;	//TB_DISABLE TB_ENABLE: TBCTR phase load on SYNC (required for updown count HR controlEPwm4Regs.TBCTL.bit.PHSDIR = TB_UP; 				// Count TB_UP on sync (=120 deg)EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;		// TB_SYNC_DISABLE TB_SYNC_INEPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;	// Clock ratio to SYSCLKOUTEPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;	// TBCLK = SYSCLKOUT / (HSPCLKDIV CLKDIV)EPwm4Regs.TBCTL.bit.FREE_SOFT = 11;EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;// Set actionsEPwm4Regs.AQCTLA.bit.CAD = AQ_SET;		// PWM toggle high/lowEPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR;EPwm4Regs.AQCTLB.bit.CBD = AQ_CLEAR;EPwm4Regs.AQCTLB.bit.CBU = AQ_SET;

///EPwm4Regs.AQSFRC.bit.RLDCSF = 3;		//AQCSFRC Active Register Reload immediately// Active Low PWMs - Setup DeadbandEPwm4Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;///DBB_ENABLE;//S1=1,S0=0
///EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HI;//S3=0,S2=0
///EPwm4Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED;//S5=1,S4=0
///EPwm4Regs.DBRED = DC_DB_TIME_300NS;// Interrupt where we will change the DeadbandEPwm4Regs.ETSEL.bit.INTSEL = ET_CTR_PRD;			// Select INT on Prd eventEPwm4Regs.ETSEL.bit.INTEN = 0;// Disable INTEPwm4Regs.ETPS.bit.INTPRD = ET_1ST;				// Generate INT on 1st event
//EALLOW;
//EPwm4Regs.HRCNFG.all = 0x0;
//EPwm4Regs.HRCNFG.bit.HRLOAD  = HR_CTR_ZERO_PRD; 		// load on CTR = 0 and CTR = TBPRD
//EPwm4Regs.HRCNFG.bit.AUTOCONV = 1;	// Enable autoconversion for HR period
//EPwm4Regs.HRCNFG.bit.EDGMODE = HR_FEP;///HR_BEP;	// MEP control on both edges
//EPwm4Regs.HRCNFG.bit.CTLMODE = HR_CMP;	// CMPAHR and TBPRDHR HR control
//
//EPwm4Regs.HRPCTL.bit.TBPHSHRLOADE = 1;	// Enable TBPHSHR sync (required for updwn count HR control)
//EPwm4Regs.HRPCTL.bit.HRPE = 1;	// Turn on high-resolution period control.
//
/////EPwm4Regs.TBCTL.bit.SWFSYNC = 1;	// Synchronize high resolution phase to start HR period
//
/////SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;// Enable TBCLK within the EPWM
//EDIS;
}

void InitEPwm5(void)
{
// ePWM channel register configuration with HRPWM
// ePWMxA toggle low/high with MEP control on Rising edgeEALLOW;CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;// Disable TBCLK within the EPWMEDIS;///EPWM5 config config for PWM2A/2BEPwm5Regs.TBCTL.bit.PRDLD = TB_SHADOW;// set Shadow loadEPwm5Regs.TBPRD = EPWM1_TIMER_TBPRD;// (60M/250k-1)=239 Set timer period-120kHz,PWM frequency = 1/(2*TBPRD)EPwm5Regs.CMPA.bit.CMPA = EPWM1_MIN_CMPA;EPwm5Regs.CMPA.bit.CMPAHR = 0;// initialize HRPWM extensionEPwm5Regs.CMPB.bit.CMPB = EPWM1_TIMER_TBPRD - EPWM1_MIN_CMPA;EPwm5Regs.CMPB.bit.CMPBHR = 0;EPwm5Regs.TBPHS.all = 0;EPwm5Regs.TBCTR = 0;// Setup TBCLKEPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count upEPwm5Regs.TBCTL.bit.PHSEN = TB_ENABLE;// Disable phase loadingEPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;// Clock ratio to SYSCLKOUTEPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV1;// TBCLK = SYSCLKOUT / (HSPCLKDIV �� CLKDIV)EPwm5Regs.TBCTL.bit.PRDLD = TB_SHADOW;EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;// PWM5ͬ��EPwm5Regs.TBCTL.bit.PHSDIR = TB_UP;EPwm5Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;// Load registers every ZEROEPwm5Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;EPwm5Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;EPwm5Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;// Setup compare// Set actionsEPwm5Regs.AQCTLA.bit.CAD = AQ_SET;// Set PWM5A on ZeroEPwm5Regs.AQCTLA.bit.CAU = AQ_CLEAR;EPwm5Regs.AQCTLB.bit.CBD = AQ_CLEAR;// Set PWM5A on ZeroEPwm5Regs.AQCTLB.bit.CBU = AQ_SET;// Active Low PWMs - Setup DeadbandEPwm5Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;//����������//EPwm5Regs.DBCTL.bit.POLSEL = DB_ACTV_LO;//EPwm5Regs.DBCTL.bit.IN_MODE = DBA_ALL;//EPwm5Regs.DBRED = EPWM1_MIN_DB;// EPwm5Regs.DBFED = EPWM1_MIN_DB;//EPwm5_DB_Direction = DB_UP;// Interrupt where we will change the DeadbandEPwm5Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;// Select INT on Prd eventEPwm5Regs.ETSEL.bit.INTEN = 1;// Enable INTEPwm5Regs.ETPS.bit.INTPRD = ET_1ST;// Generate INT on 1st event

	//ADC trigger source/*EPwm5Regs.ETSEL.bit.SOCAEN	= 1;//ʹ��ADC����ת������		// Enable SOC on A groupEPwm5Regs.ETSEL.bit.SOCASEL	= 4;//�����������ӵ�CMPAʱʹ���¼�		// Select SOC from from CPMA on upcountEPwm5Regs.ETPS.bit.SOCAPRD 	= 1;		// Generate pulse on 1st event*/
}

void InitEPwm6(void)
{
// ePWM channel register configuration with HRPWM
// ePWMxA toggle low/high with MEP control on Rising edgeEALLOW;CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;// Disable TBCLK within the EPWMEDIS;///EPWM6 config config for PWM2A/2BEPwm6Regs.TBCTL.bit.PRDLD = TB_SHADOW;// set Shadow loadEPwm6Regs.TBPRD = EPWM1_TIMER_TBPRD;// (60M/250k-1)=239 Set timer period-120kHz,PWM frequency = 1/(2*TBPRD)EPwm6Regs.CMPA.bit.CMPA = EPWM1_MIN_CMPA;EPwm5Regs.CMPA.bit.CMPAHR = 0;// initialize HRPWM extensionEPwm6Regs.CMPB.bit.CMPB = EPWM1_TIMER_TBPRD - EPWM1_MIN_CMPA;EPwm6Regs.CMPB.bit.CMPBHR = 0;EPwm6Regs.TBPHS.all = 0;EPwm6Regs.TBCTR = 0;// Setup TBCLKEPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count upEPwm6Regs.TBCTL.bit.PHSEN = TB_ENABLE;// Disable phase loadingEPwm6Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;// Clock ratio to SYSCLKOUTEPwm6Regs.TBCTL.bit.CLKDIV = TB_DIV1;// TBCLK = SYSCLKOUT / (HSPCLKDIV �� CLKDIV)EPwm6Regs.TBCTL.bit.PRDLD = TB_SHADOW;EPwm6Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;// PWM6ͬ��EPwm6Regs.TBCTL.bit.PHSDIR = TB_UP;EPwm6Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;// Load registers every ZEROEPwm6Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;EPwm6Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;EPwm6Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;// Set actionsEPwm6Regs.AQCTLA.bit.CAD = AQ_SET;EPwm6Regs.AQCTLA.bit.CAU = AQ_CLEAR;EPwm6Regs.AQCTLB.bit.CBD = AQ_CLEAR;EPwm6Regs.AQCTLB.bit.CBU = AQ_SET;// Active Low PWMs - Setup DeadbandEPwm6Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;//����������EPwm6Regs.DBCTL.bit.POLSEL = DB_ACTV_LO;//EPwm6Regs.DBCTL.bit.IN_MODE = DBA_ALL;//EPwm6Regs.DBRED = EPWM1_MIN_DB;//EPwm6Regs.DBFED = EPWM1_MIN_DB;// EPwm6_DB_Direction = DB_UP;// Interrupt where we will change the Deadband
//EPwm6Regs.ETSEL.bit.INTSEL = ET_CTR_PRD;// Select INT on Prd event
//EPwm6Regs.ETSEL.bit.INTEN = 1;// Enable INT
//EPwm6Regs.ETPS.bit.INTPRD = ET_1ST;// Generate INT on 1st event

	//ADC trigger source
//EPwm6Regs.ETSEL.bit.SOCAEN	= 1;		// Enable SOC on A group
//EPwm6Regs.ETSEL.bit.SOCASEL	= 1;		// Select SOC from from CPMA on downcount
//EPwm6Regs.ETPS.bit.SOCAPRD 	= 1;		// Generate pulse on 1st event

//EALLOW;
//CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;		// Disable TBCLK within the EPWM
//EDIS;

}
void InitEPwm7(void)
{
// ePWM channel register configuration with HRPWM
// ePWMxA toggle low/high with MEP control on Rising edgeEALLOW;CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;// Disable TBCLK within the EPWMEDIS;///EPWM2 config config for PWM2A/2BEPwm7Regs.TBCTL.bit.PRDLD = TB_SHADOW;// set Shadow loadEPwm7Regs.TBPRD = EPWM_AD_TIMER_TBPRD;// (100M/100k-1)=999 Set timer period-100kHz,PWM frequency = 1/(2*TBPRD)EPwm7Regs.CMPA.bit.CMPA = EPWM1_MIN_CMPA;EPwm7Regs.CMPA.bit.CMPAHR = 0;// initialize HRPWM extensionEPwm7Regs.CMPB.bit.CMPB = EPWM1_TIMER_TBPRD - EPWM1_TIMER_TBPRD;EPwm7Regs.CMPB.bit.CMPBHR = 0;EPwm7Regs.TBPHS.all = 0;EPwm7Regs.TBCTR = 0;// Setup TBCLKEPwm7Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;//TB_COUNT_UPDOWN TB_COUNT_UP; // Select up-down count modeEPwm7Regs.TBCTL.bit.PHSEN = TB_ENABLE;// TB_ENABLE TB_DISABLE: TBCTR phase load on SYNC (required for updown count HR controlEPwm7Regs.TBCTL.bit.PHSDIR = TB_UP;// Count TB_UP on syncEPwm7Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;// pass onEPwm7Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;// Clock ratio to SYSCLKOUTEPwm7Regs.TBCTL.bit.CLKDIV = TB_DIV1;// TBCLK = SYSCLKOUT / (HSPCLKDIV CLKDIV)EPwm7Regs.TBCTL.bit.FREE_SOFT = 11;//TBPRD is loaded from its shadow register on Counter = 0 event (CTR_zero)EPwm7Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;//CC_CTR_ZERO_PRD;EPwm7Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;//CC_CTR_ZERO_PRD;EPwm7Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;EPwm7Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;EPwm7Regs.AQCTLA.bit.CAD = AQ_SET;//���������ظ߾���Ϊ�½��ظ߾���EPwm7Regs.AQCTLA.bit.CAU = AQ_CLEAR; //���������ظ߾���Ϊ�½��ظ߾���
///EPwm1Regs.AQSFRC.bit.RLDCSF = 3;//AQCSFRC Active Register Reload immediately//Setup DeadbandEPwm7Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;///DBB_ENABLE;//S1=1,S0=0
///EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HI;//S3=0,S2=0
///EPwm1Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED;//S5=1,S4=0
///EPwm1Regs.DBRED = DC_DB_TIME_300NS;//DC_DB_TIME_300NS;// Interrupt where we will change the DeadbandEPwm7Regs.ETSEL.bit.INTSEL = 0;// Select INT on Zero & PRD eventEPwm7Regs.ETSEL.bit.INTEN = 0;// Disable INTEPwm7Regs.ETPS.bit.INTPRD = ET_1ST;// Generate INT on 1st eventEPwm7Regs.ETSEL.bit.SOCAEN = 1;//Eables SOCA pulseEPwm7Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO;//20121008//ET_CTR_PRD;//ET_CTR_ZERO;//Enable CNTR = zero eventEPwm7Regs.ETPS.bit.SOCAPRD = ET_1ST;// Generate pulse on 1st event

//EALLOW;
//EPwm7Regs.HRCNFG.all = 0x0;
//EPwm7Regs.HRCNFG.bit.HRLOAD  = HR_CTR_ZERO_PRD;//HR_CTR_ZERO_PRD load COMPAHR on CTR = 0 and CTR = TBPRD;HR_CTR_ZERO_PRD
//EPwm7Regs.HRCNFG.bit.AUTOCONV = 1;// Enable autoconversion for HR period
//EPwm7Regs.HRCNFG.bit.EDGMODE = HR_BEP;// MEP control on both edges
//EPwm7Regs.HRCNFG.bit.CTLMODE = HR_CMP;// CMPAHR and TBPRDHR HR control
//
//EPwm7Regs.HRPCTL.bit.TBPHSHRLOADE = 1;// Enable TBPHSHR sync (required for updwn count HR control)
//EPwm7Regs.HRPCTL.bit.HRPE = 1;// Turn on high-resolution period control.
//
/////SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;// Enable TBCLK within the EPWM
/////EPwm1Regs.TBCTL.bit.SWFSYNC = 1;// Synchronize high resolution phase to start HR period
//
//EDIS;

}

void InitEPwm8(void)
{
// ePWM channel register configuration with HRPWM
// ePWMxA toggle low/high with MEP control on Rising edgeEALLOW;CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;// Disable TBCLK within the EPWMEDIS;///EPWM8 config config for PWM2A/2BEPwm8Regs.TBCTL.bit.PRDLD = TB_SHADOW;// set Shadow loadEPwm8Regs.TBPRD = EPWM1_TIMER_TBPRD;// (60M/250k-1)=239 Set timer period-120kHz,PWM frequency = 1/(2*TBPRD)EPwm8Regs.CMPA.bit.CMPA = EPWM1_MIN_CMPA;EPwm8Regs.CMPA.bit.CMPAHR = 0;// initialize HRPWM extensionEPwm8Regs.CMPB.bit.CMPB = 0x3E7;//EPwm8Regs.CMPB.bit.CMPBHR = 0;EPwm8Regs.TBPHS.all = 0;EPwm8Regs.TBCTR = 0;// Setup TBCLKEPwm8Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;//TB_COUNT_UPDOWN TB_COUNT_UP; // Select up-down count modeEPwm8Regs.TBCTL.bit.PHSEN = TB_ENABLE;// TB_ENABLE TB_DISABLE: TBCTR phase load on SYNC (required for updown count HR controlEPwm8Regs.TBCTL.bit.PHSDIR = TB_UP;// Count TB_UP on syncEPwm8Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;// pass onEPwm8Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;// Clock ratio to SYSCLKOUTEPwm8Regs.TBCTL.bit.CLKDIV = TB_DIV1;// TBCLK = SYSCLKOUT / (HSPCLKDIV CLKDIV)EPwm8Regs.TBCTL.bit.FREE_SOFT = 11;//TBPRD is loaded from its shadow register on Counter = 0 event (CTR_zero)EPwm8Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;//CC_CTR_ZERO_PRD;EPwm8Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;//CC_CTR_ZERO_PRD;EPwm8Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;EPwm8Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;EPwm8Regs.AQCTLB.bit.CBD = AQ_SET;EPwm8Regs.AQCTLB.bit.CBU = AQ_CLEAR;//Setup DeadbandEPwm8Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;///DBB_ENABLE;//S1=1,S0=0
///EPwm8Regs.DBCTL.bit.POLSEL = DB_ACTV_HI;//S3=0,S2=0
///EPwm8Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED;//S5=1,S4=0
///EPwm8Regs.DBRED = DC_DB_TIME_300NS;//DC_DB_TIME_300NS;// Interrupt where we will change the DeadbandEPwm8Regs.ETSEL.bit.INTSEL = 0;// Select INT on Zero & PRD eventEPwm8Regs.ETSEL.bit.INTEN = 0;// Disable INTEPwm8Regs.ETPS.bit.INTPRD = ET_1ST;// Generate INT on 1st event

//EALLOW;
//EPwm8Regs.HRCNFG.all = 0x0;
//EPwm8Regs.HRCNFG.bit.HRLOAD  = HR_CTR_ZERO_PRD;//HR_CTR_ZERO_PRD load COMPAHR on CTR = 0 and CTR = TBPRD;HR_CTR_ZERO_PRD
//EPwm8Regs.HRCNFG.bit.AUTOCONV = 1;// Enable autoconversion for HR period
//EPwm8Regs.HRCNFG.bit.EDGMODE = HR_BEP;// MEP control on both edges
//EPwm8Regs.HRCNFG.bit.CTLMODE = HR_CMP;// CMPAHR and TBPRDHR HR control
//
//EPwm8Regs.HRPCTL.bit.TBPHSHRLOADE = 1;// Enable TBPHSHR sync (required for updwn count HR control)
//EPwm8Regs.HRPCTL.bit.HRPE = 1;// Turn on high-resolution period control.
//
/////SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;// Enable TBCLK within the EPWM
/////EPwm1Regs.TBCTL.bit.SWFSYNC = 1;// Synchronize high resolution phase to start HR period
//
//EDIS;EALLOW;CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;// Disable TBCLK within the EPWMEDIS;
}
//===========================================================================
// End of file.
//===========================================================================