TI中文支持网Part Number:TMS320F28035
Hi Professor，
I am debugging the phase shift full-bridge BUCK circuit based on F28035 chip, and realize phase shift by using peak current control. I use EPWM2 as the driver of arm, EPWM1 as the hysteresis arm, EPWM3 as the driver of side-side synchronous rectification, EPWM4 as the trigger ADC sampling, and COMP3A as the detection of peak current.Synchronize the EPWM2 clock at the same time to achieve phase shift.
However, the COMP3A comparator event cannot be triggered at the moment of low current, so the phase shift of EPWM2 cannot be realized.
我正在调试基于F28035芯片的移相全桥BUCK电路，使用峰值电流控制实现移相，我使用EPWM2作为超前臂的驱动，使用EPWM1作为滞后臂，使用EPWM3作为副边同步整流的驱动，使用EPWM4触发ADC采样，使用COMP3A作为峰值电流的检测，同时同步EPWM2时钟，来实现移相。
但是目前无法在小电流的时候触发COMP3A的比较器事件，无法实现EPWM2的移相？
EPWM2 module configuration is as follows:
#define HSFB_PERIOD 205 //146kHz
void PWM_Config(void)
{
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the EPWM
EDIS;
//Time Base SubModule Register
EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // Set Immediate load
EPwm1Regs.TBPRD = HSFB_PERIOD;
EPwm1Regs.TBPHS.half.TBPHS = 0;
EPwm1Regs.TBCTR = 0;
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_CMPB; // Used to sync EPWM(n+1) "down-stream"
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// Counter compare submodule registers
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE;
EPwm1Regs.CMPA.half.CMPA = HSFB_PERIOD-68;//trig_up;ynj
EPwm1Regs.CMPB = HSFB_PERIOD;
// Action Qualifier SubModule Registers
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;
EPwm1Regs.AQCTLA.bit.PRD = AQ_CLEAR;
// DeadBand Control Register
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi Complimentary
EPwm1Regs.DBRED = 6; // Initial value
EPwm1Regs.DBFED = 6; // Initial value
// ePWM(n+1) init. EPWM(n+1) is a slave
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBPRD = HSFB_PERIOD-1;
EPwm2Regs.TBPHS.half.TBPHS = 0;
EPwm2Regs.TBCTR = 0;
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Sync "flow through" mode
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// Counter compare submodule registers
EPwm2Regs.CMPA.half.CMPA = HSFB_PERIOD + 10; // Initial valueynj
EPwm2Regs.CMPB = 20; // Initial value ynj
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
// Action Qualifier SubModule Registers
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;//AQ_CLEAR;ynj
EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR;
EPwm2Regs.AQCTLA.bit.CBU = AQ_CLEAR;//AQ_SET;
EPwm2Regs.AQCTLA.bit.PRD = AQ_CLEAR;
EPwm2Regs.AQCTLB.bit.CBU = AQ_SET;
EPwm2Regs.AQCTLB.bit.ZRO = AQ_CLEAR;//AQ_CLEAR;
EPwm2Regs.AQCTLB.bit.CAU = AQ_CLEAR;
EPwm2Regs.AQCTLB.bit.PRD = AQ_CLEAR;
// Peak current control configure.
EALLOW;
//===========================================================================
// Define an event (DCAEVT1) based on Comparator 1 Output
EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_COMP3OUT; // DCAH = Comparator 1 output
EPwm2Regs.TZDCSEL.bit.DCAEVT1 = TZ_DCAH_HI; // DCAEVT1 = DCAH high(will become active
// as Comparator output goes high)
EPwm2Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT1;//DC_EVT_FLT; // DCAEVT1 = DC_EVT_FLT (filtered)
EPwm2Regs.DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC; // Take async path
// EPwm2Regs.TBCTL.bit.SWFSYNC =1;
// EPwm2Regs.TBCTL.bit.PRDLD=1;
// Enable DCAEVT1 as a one-shot sourceEPwm2Regs.TZFLG.bit.DCAEVT1
EPwm2Regs.TZSEL.bit.DCAEVT1 = 1; // Enable One-Shot Trip
// Following code for the sync mechanism based on the same trigger event – COMPxOUT
EPwm2Regs.DCACTL.bit.EVT1SYNCE = 1; // Sync enabled
// What do we want the DCAEVT1 event to do? – Initial Configuration
EPwm2Regs.TZCTL.bit.TZA = TZ_NO_CHANGE; // EPWMxA – no change
EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO;//TZ_NO_CHANGE; // EPWMxB – go low
// EPwm2Regs.TZCTL.bit.DCAEVT1 = TZ_NO_CHANGE;//YNJ
//===========================================================================
// Event Filtering Configuration
EPwm2Regs.DCFCTL.bit.SRCSEL = DC_SRC_DCAEVT1;
EPwm2Regs.DCFCTL.bit.BLANKE = DC_BLANK_ENABLE;
EPwm2Regs.DCFCTL.bit.PULSESEL = DC_PULSESEL_ZERO;
// EPwm2Regs.DCFOFFSET = 2; // Blanking Window Offset = CMPA(n+1)
// EPwm2Regs.DCFWINDOW = 4; // Blanking window length – initial value
//===========================================================================
EDIS;
//Time Base SubModule Register
EPwm3Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE;
EPwm3Regs.TBPRD = HSFB_PERIOD-35;
EPwm3Regs.TBPHS.half.TBPHS = 0;
EPwm3Regs.TBCTR = 0;
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;
EPwm3Regs.TBCTL.bit.PHSDIR = TB_UP;
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass the Sync signal through to ePWM4
EPwm3Regs.CMPA.half.CMPA = HSFB_PERIOD/2 – 10; // Initial value
// Action Qualifier SubModule Registers
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET;
EPwm3Regs.AQCTLB.bit.CAU = AQ_CLEAR;
EPwm3Regs.AQCTLB.bit.ZRO = AQ_SET;
//Configure EPWM4 time base for ADC SOC generation and syncing the DAC
//Configure EPWM(n+2) time base for ADC SOC generation and syncing the DAC
//Time Base SubModule Register
EPwm4Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE;
EPwm4Regs.TBPRD = HSFB_PERIOD-1;
EPwm4Regs.TBPHS.half.TBPHS = HSFB_PERIOD-35;
EPwm4Regs.TBCTR = 0;
EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE;
EPwm4Regs.TBCTL.bit.PHSDIR = TB_UP;
EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass the Sync signal through to ePWM4
// ADC SOC generation
//===========================================================================
// SOC generation using PWM(n) – 1st of 4 Vout conversions in one half cycle
EPwm1Regs.ETSEL.bit.SOCAEN = 1;
EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTR_PRDZERO; // Use ZRO and PRD events as trigger
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
// SOC generation using PWM(n+1) – Iout conversion
EPwm2Regs.ETSEL.bit.SOCAEN = 1;
EPwm2Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO; // Use ZRO event as trigger
EPwm2Regs.ETPS.bit.SOCAPRD = ET_2ND; // Generate pulse on 1st event
// SOC generation using PWM(n+2) – 2nd, 3rd and 4th Vout conversions in one half cycle; Vin and Ipri conversions
EPwm4Regs.ETSEL.bit.SOCAEN = 1;
EPwm4Regs.ETSEL.bit.SOCASEL = ET_CTRU_CMPA; // Use CAU event as trigger
EPwm4Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm4Regs.CMPA.half.CMPA = 40; // Note: This value is based on 100 KHz switching frequency
EPwm4Regs.ETSEL.bit.SOCBEN = 1;
EPwm4Regs.ETSEL.bit.SOCBSEL = ET_CTRU_CMPB; // Use CBU event as trigger
EPwm4Regs.ETPS.bit.SOCBPRD = 1; // Generate pulse on 1st event
EPwm4Regs.CMPB = 165; // Note: This value is based on 100 KHz switching frequency
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
/*—————————————–*/
}
COMP3A configuration is as follows:
EALLOW;
AdcRegs.COMPHYSTCTL.bit.COMP3_HYST_DISABLE=0;
EDIS;
EALLOW;
GpioCtrlRegs.AIOMUX1.bit.AIO6 = 2;
EDIS;
EALLOW;
Comp3Regs.COMPCTL.bit.COMPDACEN = 1; // Power up Comparator locally
Comp3Regs.COMPCTL.bit.COMPSOURCE = 0; // Connect the inverting input to internal DAC
Comp3Regs.DACVAL.bit.DACVAL = 500; // Set DAC output – Input is Q15 – Convert to Q10
Comp3Regs.DACCTL.bit.DACSOURCE = 1; // 0 – DACVAL; 1 – Internal ramp for slope compensation
// Following lines of code are used when internal slope compensation is used
Comp3Regs.COMPCTL.bit.QUALSEL =5; // Comparator output must be active for 4 consecutive clocks before resetting the RAMP
Comp3Regs.DACCTL.bit.RAMPSOURCE = 3; // 0 – PMW1; 1 – PWM2, 2-PWM3, 3-PWM4
Comp3Regs.RAMPDECVAL_SHDW = 40;
EPwm4Regs.HRPCTL.bit.PWMSYNCSEL = 1; // PWM SYNC generated at CTR = ZRO for synchronizing internal ramp
Comp3Regs.COMPCTL.bit.CMPINV = 0; // Comparator Output passed
EDIS;
The interrupt function is as follows:
#define DACDRV_RAMP_In 38400 //环路计算值
if(TB_DIR_UP == EPwm1Regs.TBSTS.bit.CTRDIR) //PWM counter direction is UP
{
EPwm2Regs.TZCLR.all |= 0x0C;
EPwm2Regs.TZCTL.all = 0x0FFF;//0x0FFB; //Force EPWMxB to a low state
EPwm2Regs.AQCTLB.all = 0x0215; //CBU=HIGH, CAU=LOW, PRD=LOW, ZERO=LOW
EPwm2Regs.AQCTLA.all = 0x0124; //CBU=LOW, CAU=HIGH, PRD=LOW, ZERO=Nothing
EPwm2Regs.CMPA.half.CMPA = DB_AtoP;
EPwm2Regs.CMPB = (HSFB_PERIOD);
EPwm2Regs.DCFWINDOW = DB_PtoA+3;
EPwm1Regs.CMPA.half.CMPA = trig_up;
EPwm1Regs.CMPB = (HSFB_PERIOD+10); //set to 0, avoid CMPB to force EPWM2 sync event. Use DCAEVT1.sync to sync EPwm2 module.
EPwm1Regs.ETSEL.all=0x0B0D;
//Update RAMP value.
Comp3Regs.RAMPMAXREF_SHDW = DACDRV_RAMP_In; //Q16 type, max value is 0xFFFF;
Comp3Regs.DACVAL.all = (DACDRV_RAMP_In>>6); //Q10 type
}
else //PWM counter direction is DOWN
{
EPwm2Regs.TZCLR.all |= 0x0C;
EPwm2Regs.TZCTL.all = 0x0FFF;//0x0FFE; //Force EPWMxA to a low state
EPwm2Regs.AQCTLA.all = 0x0125; //CBU=LOW, CAU=HIGH,PRD=LOW, ZERO=LOW
EPwm2Regs.AQCTLB.all = 0x0214; //CBU=HIGH,CAU=LOW, PRD=LOW, ZER0=Nothing
EPwm2Regs.CMPB = DB_AtoP;
EPwm2Regs.CMPA.half.CMPA = (HSFB_PERIOD);
EPwm2Regs.DCFWINDOW = DB_PtoA+3; //Need confirm
EPwm1Regs.CMPA.half.CMPA = trig_dwn;
EPwm1Regs.CMPB = HSFB_PERIOD+10; //set to period, avoid CMPB to force EPWM2 sync event. Use DCAEVT1.sync to sync EPwm2 module.
EPwm1Regs.ETSEL.all = 0x0B0C;
}
Does the above configuration change the phase shift Angle by changing the value of DACDRV_RAMP_In?
以上配置，是否通过改变DACDRV_RAMP_In，来改变移相角大小?
Green Deng：
你好，为你将问题升级到英文版E2E了，还请留意以下帖子的工程师回复：e2e.ti.com/…/tms320f28035-the-phase-shifted-full-bridge-problem-of-psfb-peak-current-control-based-on-tms320ff28035
