TI中文支持网Part Number:TMS320F28377DOther Parts Discussed in Thread:C2000WARE
考虑可能时FPUmathtalbes的问题，请问怎么解决？
Green Deng：
看看FPUmathtalbes的定义是否正确？
可以参考下面的代码，路径为C:\ti\c2000\C2000Ware_3_01_00_00\libraries\dsp\FPU\c28\examples\common\f2837xd
例程路径为 C:\ti\c2000\C2000Ware_3_01_00_00\libraries\dsp\FPU\c28\examples\fft\2837x_rfft_adc
//############################################################################# // // FILE:F2837xD_FPU_RFFT_ADC_lnk.cmd // // TITLE:Linker Command File for FPU library examples that run//on the 2837x platform // //This file includes all RAM and FLASH blocks present on the //2837x and depending on the active build configuration(RAM or FLASH) //the appropriate sections will either be loaded into RAM or FLASH//blocks // //############################################################################# // $TI Release: C28x Floating Point Unit Library V2.03.00.00 $ // $Release Date: Mar 19, 2020 $ // $Copyright: Copyright (C) 2018 Texas Instruments Incorporated - //https://www.ti2k.com/wp-content/uploads/ti2k/DeyiSupport_C2000_ ALL RIGHTS RESERVED $ //############################################################################# // NOTES: // 1. In addition to this memory linker command file, add the header linker//command file directly to the project. The header linker command file is//required to link the peripheral structures to the proper locations within //the memory map. ////The header linker files are found in//c2000\C2000Ware_X_XX_XX_XX\device_support\f2837x(d/s)\headers\cmd ////For BIOS applications add:F2837x(D/S)_Headers_BIOS_cpuX.cmd //For nonBIOS applications add:F2837x(D/S)_Headers_nonBIOS_cpuX.cmd // // 2. On reset all RAMGSx blocks are under the mastership of CPU1. The user //must configure the appropriate control registers to transfer mastership //of a RAMGSx block over to CPU2 // // 3. Memory blocks on F2837x are uniform (ie same physical memory) in both//PAGE 0 and PAGE 1. That is the same memory region should not be defined//for both PAGE 0 and PAGE 1. Doing so will result in corruption of program //and/or data. ////Contiguous SARAM memory blocks can be combined if required to create a//larger memory block. // //#############################################################################// The following definitions will help to align the input buffer.For the complex FFT // of size N, the input buffer must be aligned to a 4N word boundary. For a real FFT // of size N, the input buffer must be aligned to a 2N word boundary. The user may define // the macro either in the linker command file, as shown here, or // through the project properties under, // C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define --define RFFT_ALIGNMENT=1024 #if !defined(RFFT_ALIGNMENT) #error define RFFT_ALIGNMENT under C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define #endifMEMORY { PAGE 0 :/* BEGIN is used for the "boot to SARAM" bootloader mode*/ #if defined(RAM)BEGIN: origin = 0x000000, length = 0x000002 #elif defined(FLASH)BEGIN: origin = 0x080000, length = 0x000002 #endifRAMM0: origin = 0x000122, length = 0x0002DERAMM1: origin = 0x000400, length = 0x000400RAMD0: origin = 0x00B000, length = 0x000800RAMD1: origin = 0x00B800, length = 0x000800RAMLS0: origin = 0x008000, length = 0x000800RAMLS1: origin = 0x008800, length = 0x000800RAMLS2: origin = 0x009000, length = 0x000800RAMGS0: origin = 0x00C000, length = 0x001000RAMGS1: origin = 0x00D000, length = 0x001000RAMGS2: origin = 0x00E000, length = 0x001000RAMGS3: origin = 0x00F000, length = 0x001000RESET: origin = 0x3FFFC0, length = 0x000002FLASHA: origin = 0x080002, length = 0x001FFE /* on-chip Flash */FLASHC: origin = 0x084000, length = 0x002000 /* on-chip Flash */FLASHD: origin = 0x086000, length = 0x002000 /* on-chip Flash */FLASHE: origin = 0x088000, length = 0x008000 /* on-chip Flash */FLASHF: origin = 0x090000, length = 0x008000 /* on-chip Flash */FLASHG: origin = 0x098000, length = 0x008000 /* on-chip Flash */FLASHH: origin = 0x0A0000, length = 0x008000 /* on-chip Flash */FLASHI: origin = 0x0A8000, length = 0x008000 /* on-chip Flash */FLASHJ: origin = 0x0B0000, length = 0x008000 /* on-chip Flash */FLASHK: origin = 0x0B8000, length = 0x002000 /* on-chip Flash */FLASHL: origin = 0x0BA000, length = 0x002000 /* on-chip Flash */FLASHM: origin = 0x0BC000, length = 0x002000 /* on-chip Flash */FLASHN: origin = 0x0BE000, length = 0x002000 /* on-chip Flash */PAGE 1 :BOOT_RSVD: origin = 0x000002, length = 0x000120/* Part of M0, BOOT rom will use this for stack */RAMLS3: origin = 0x009800, length = 0x000800RAMLS4: origin = 0x00A000, length = 0x000800RAMLS5: origin = 0x00A800, length = 0x000800RAMGS45: origin = 0x010000, length = 0x002000RAMGS67: origin = 0x012000, length = 0x002000RAMGS89: origin = 0x014000, length = 0x002000RAMGS1011: origin = 0x016000, length = 0x002000RAMGS12: origin = 0x018000, length = 0x001000RAMGS13: origin = 0x019000, length = 0x001000RAMGS14: origin = 0x01A000, length = 0x001000RAMGS15: origin = 0x01B000, length = 0x001000FLASHB: origin = 0x082000, length = 0x002000 /* on-chip Flash */}SECTIONS {codestart: > BEGIN,PAGE = 0 #if defined(RAM).TI.ramfunc: > RAMM0,PAGE = 0.text:>> RAMM1 | RAMD0 | RAMD1 | RAMLS0,PAGE = 0.cinit: > RAMLS1,PAGE = 0.pinit: > RAMLS1,PAGE = 0.switch: > RAMLS1,PAGE = 0.econst: > RAMLS4,PAGE = 1 #elif defined(FLASH).TI.ramfunc:LOAD = FLASHC,RUN = RAMLS1,RUN_START(_RamfuncsRunStart),LOAD_START(_RamfuncsLoadStart),LOAD_SIZE(_RamfuncsLoadSize),PAGE = 0.text: > FLASHN,PAGE = 0.cinit: > FLASHM,PAGE = 0.pinit: > FLASHM,PAGE = 0.switch: > FLASHM,PAGE = 0.econst: > FLASHB,PAGE = 1 #else #error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define #endif //RAM/* Test specific sections */RFFTdata1: > RAMGS45,PAGE = 1, ALIGN = RFFT_ALIGNMENTRFFTdata2: > RAMGS67,PAGE = 1RFFTdata3: > RAMGS89,PAGE = 1RFFTdata4: > RAMGS1011, PAGE = 1FPUmathTables: > RAMGS12,PAGE = 1.reset: > RESET,PAGE = 0, TYPE = DSECT /* not used, */.cio: > RAMLS3,PAGE = 1.sysmem: > RAMLS3,PAGE = 1.stack: > RAMLS4,PAGE = 1.ebss: > RAMLS5,PAGE = 1.esysmem: > RAMLS4,PAGE = 1} /* //=========================================================================== // End of file. //=========================================================================== */
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Rou W：
MEMORY{PAGE 0 : /* Program Memory */ /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */ /* BEGIN is used for the "boot to Flash" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002 RAMM0 : origin = 0x000122, length = 0x0002DE RAMD0 : origin = 0x00B000, length = 0x000800 RAMLS03 : origin = 0x008000, length = 0x003000/* RAMLS0 : origin = 0x008000, length = 0x000800 RAMLS1 : origin = 0x008800, length = 0x000800 RAMLS2 : origin = 0x009000, length = 0x000800 RAMLS3 : origin = 0x009800, length = 0x000800 RAMLS4 : origin = 0x00A000, length = 0x000800*/
RAMGS6 : origin = 0x012000, length = 0x001000 RAMGS7 : origin = 0x013000, length = 0x001000 RAMGS8 : origin = 0x014000, length = 0x001000 RAMGS9 : origin = 0x015000, length = 0x001000 RAMGS10 : origin = 0x016000, length = 0x001000 RAMGS11 : origin = 0x017000, length = 0x001000 RESET : origin = 0x3FFFC0, length = 0x000002 /* Flash sectors */ FLASH_API : origin = 0x080004, length = 0x000FFC /* on-chip FLASH */ FLASH_ASM : origin = 0x081000, length = 0x000080 /*commented by ivan @121111*/ FLASH_ENTER : origin = 0x081080, length = 0x000080 FLASH_CODE1 : origin = 0x081100, length = 0x000F00// FLASHA : origin = 0x080004, length = 0x001FFC /* on-chip Flash */ FLASH_BEGIN : origin = 0x082000, length = 0x000004 /* on-chip Flash */ FLASHB : origin = 0x082004, length = 0x001FFC /* on-chip Flash */ FLASHC : origin = 0x084000, length = 0x004000 /* on-chip Flash */ /*FLASHD : origin = 0x086000, length = 0x002000*/ /* on-chip Flash */ FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ FLASHN : origin = 0x0BE000, length = 0x001FD0 /* on-chip Flash */ FLASH_LINK : origin = 0x0BFFD0, length = 0x00002C FLASH_END : origin = 0x0BFFFC, length = 0x000004 //align(4) lead to this
// FLASHM : origin = 0x0BC000, length = 0x001FD0 /* on-chip Flash */// FLASH_LINK : origin = 0x0BDFD0, length = 0x00002C// FLASH_END : origin = 0x0BDFFC, length = 0x000004 //align(4) lead to this// FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
PAGE 1 : /* Data Memory */ /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ RAMD1 : origin = 0x00B000, length = 0x001000
//RAMLS5 : origin = 0x00A800, length = 0x000800
RAMGS0 : origin = 0x00C000, length = 0x003000 /*test*/// RAMGS1 : origin = 0x00D000, length = 0x001000 RAMGS2 : origin = 0x00F000, length = 0x000C00 RAMGS3 : origin = 0x00FC00, length = 0x000C00 RAMGS4 : origin = 0x010800, length = 0x000C00 RAMGS5 : origin = 0x011400, length = 0x000C00 RAMGS12 : origin = 0x018000, length = 0x002000// FLASHF : origin = 0x090000, length = 0x002000 /* on-chip Flash */
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400}
SECTIONS{ /* Allocate program areas: */ .cinit : > FLASHB PAGE = 0 , ALIGN(4) .pinit : > FLASHB, PAGE = 0 , ALIGN(4) .text : >> FLASHE| FLASHG| FLASHH| FLASHI PAGE = 0 , ALIGN(4) //.text : >> FLASHE| FLASHF| FLASHG| FLASHH| FLASHI PAGE = 0 , ALIGN(4) // .text : > FLASHB PAGE = 0 , ALIGN(4) codestart : > BEGIN PAGE = 0 , ALIGN(4)/* ramfuncs : LOAD = FLASHD, RUN = RAMLS03,//RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, LOAD_START(_RamfuncsLoadStart), LOAD_SIZE(_RamfuncsLoadSize), LOAD_END(_RamfuncsLoadEnd), RUN_START(_RamfuncsRunStart), RUN_SIZE(_RamfuncsRunSize), RUN_END(_RamfuncsRunEnd), PAGE = 0 , ALIGN(4)*/ ramfuncs : LOAD = FLASHC, RUN = RAMLS03 ,//RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, LOAD_START(_RamfuncsLoadStart), LOAD_SIZE(_RamfuncsLoadSize), LOAD_END(_RamfuncsLoadEnd), RUN_START(_RamfuncsRunStart), RUN_SIZE(_RamfuncsRunSize), RUN_END(_RamfuncsRunEnd), PAGE = 0 , ALIGN(4)
OSStack : > RAMD1 , PAGE = 1 /* Allocate uninitalized data sections: */ .stack : > RAMM1 PAGE = 1/* .ebss : >> RAMLS5 | RAMGS0 | RAMGS1 PAGE = 1*/ .ebss : > RAMGS0 PAGE = 1 /*.esysmem : > RAMLS5 PAGE = 1*/ .esysmem : > RAMGS2 PAGE = 1
/* Initalized sections go in Flash */ .econst : >> FLASHJ | FLASHK | FLASHL PAGE = 0, ALIGN(4) .switch : > FLASHM PAGE = 0, ALIGN(4)
FPUmathTables : > RAMGS12, PAGE = 1
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
IAPKEY2 : > FLASH_BEGIN , PAGE = 0, ALIGN(4) IAPKEY : > FLASH_END , PAGE = 0, ALIGN(4) IAPLINK : > FLASH_LINK , PAGE = 0, ALIGN(4) IAPCODE1 : > FLASH_CODE1, PAGE = 0, ALIGN(4) IAPASM : > FLASH_ASM , PAGE = 0, ALIGN(4)// IAPCODE2 : > FLASH_CODE2, PAGE = 0, ALIGN(4) IAPENTER : > FLASH_ENTER, PAGE = 0, ALIGN(4) IAPAPIDATA : > FLASHL , PAGE = 0, ALIGN(4)
GROUP : LOAD = FLASH_API, RUN = RAMGS8, LOAD_START(_RamfuncsIapLoadStart), LOAD_SIZE(_RamfuncsIapLoadSize), LOAD_END(_RamfuncsIapLoadEnd), RUN_START(_RamfuncsIapRunStart), RUN_SIZE(_RamfuncsIapRunSize), RUN_END(_RamfuncsIapRunEnd), PAGE = 0, ALIGN(4) { IapConst ramfuncsIap }
FLASHTEST2 : > FLASHE , PAGE = 0, ALIGN(4) FLASHTEST3 : > FLASHG , PAGE = 0, ALIGN(4) FLASHTEST4 : > FLASHH , PAGE = 0, ALIGN(4) FLASHTEST5 : > FLASHI , PAGE = 0, ALIGN(4) FLASHTEST6 : > FLASHJ , PAGE = 0, ALIGN(4) FLASHTEST7 : > FLASHK , PAGE = 0, ALIGN(4) FLASHTEST8 : > FLASHM , PAGE = 0, ALIGN(4) FLASHTEST9 : > FLASHN , PAGE = 0, ALIGN(4)
// FPUmathTables : > RAMGS7, PAGE = 0 // FPUmathTables : > FLASHF, PAGE = 0
FPUmath : LOAD = FLASHF, RUN = RAMGS7, //RUN_START(_FPUmathTablesRunStart), // LOAD_START(_FPUmathTablesLoadStart), //LOAD_SIZE(_FPUmathTablesLoadSize), //PAGE = 1 LOAD_START(_FPUmathLoadStart), LOAD_END(_FPUmathLoadEnd), RUN_START(_FPUmathRunStart), PAGE = 0, ALIGN(4) { -l rts2800_fpu32_fast_supplement.lib(.text) }
Filter_RegsFile : > RAMGS0, PAGE = 1
SHARERAMGS0 : > RAMGS2, PAGE = 1 SHARERAMGS1 : > RAMGS3, PAGE = 1 VectorBuff : > RAMGS4, PAGE = 1 DataBuff : > RAMGS5, PAGE = 1 /* The following section definitions are required when using the IPC API Drivers */ GROUP : > CPU1TOCPU2RAM, PAGE = 1 { PUTBUFFER PUTWRITEIDX GETREADIDX } GROUP : > CPU2TOCPU1RAM, PAGE = 1 { GETBUFFER : TYPE = DSECT GETWRITEIDX : TYPE = DSECT PUTREADIDX : TYPE = DSECT }
}
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Rou W：
完善了一下FPUamthtables设置，但仍然是在线仿真可以，掉电重启在flas里无法正常运行
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Green Deng：
请问一下“在flash里无法正常运行”具体现象是什么样的？能否判断芯片是完全没运行还是运行到某一段代码后停住了？
