Xintf配置更改对外部SRAM的影响

    /********** zone6 for external SRAM ***********/

    XintfRegs.XTIMING6.bit.XWRLEAD = 3;   /* write lead time is 3*6.67ns=20ns */

    XintfRegs.XTIMING6.bit.XWRACTIVE = 7; /* write active time is (7+1)*6.67ns=50ns */

    XintfRegs.XTIMING6.bit.XWRTRAIL = 3;  /* write trail time is 3*6.67ns=20ns */

 

    XintfRegs.XTIMING6.bit.XRDLEAD = 3;   /* read lead time is 3*6.67ns=20ns */

    XintfRegs.XTIMING6.bit.XRDACTIVE = 7; /* read active time is (7+1)*6.67ns=50ns */

    XintfRegs.XTIMING6.bit.XRDTRAIL = 3;  /* read trail time is 3*6.67ns=20ns

 

    XintfRegs.XTIMING6.bit.X2TIMING = 0;

    XintfRegs.XTIMING6.bit.USEREADY = 0;

    XintfRegs.XTIMING6.bit.READYMODE = 0;

    XintfRegs.XTIMING6.bit.XSIZE = 3;

写整个SRAM时间为180ms,读整个SRAM时间为343ms(带校验)。

然后想缩短这个时间，把配置更改如下

    XintfRegs.XTIMING6.bit.XWRLEAD = 1; 

    XintfRegs.XTIMING6.bit.XWRACTIVE = 2；

    XintfRegs.XTIMING6.bit.XWRTRAIL = 1;  

 

    XintfRegs.XTIMING6.bit.XRDLEAD = 1;   

    XintfRegs.XTIMING6.bit.XRDACTIVE =3; 

    XintfRegs.XTIMING6.bit.XRDTRAIL = 0；  

写整个SRAM时间为180ms,没有改变。读整个SRAM时间为280ms(带校验)。

试过好几次，SRAM的写时间都没有减少，请问有什么理论可以支持这一测试结果么，谢谢！