TI中文支持网使用CCS 9.1.0版本，
调试器选择XDS100v3，在advanced界面没有JTAG/SWD/cJTAG模式选择
调试器选择XDS110，在advanced界面有JTAG/SWD/cJTAG模式选择
请问使用调试器选择XDS100v3，有没有cJTAG功能，如何进入cJTAG烧写模式？
Susan Yang：
您现在是自己设计的板子？XDS100v3是可以支持cJTAG功能的
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user4678620：
自己设计的板子，XDS100v3在CCS中怎么选择使用JTAG模式还是cJTAG模式，在哪个界面操作？
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Susan Yang：
您可以自己添加一下
1 在 ccs\ccs_base\common\targetdb\connections内找到 TIXDS100v3_Dot7_Connection
2 在其中添加
<property id="SWD Mode Settings" desc="JTAG / SWD / cJTAG Mode" Type="choicelist" Value="0" ID="DOT7.DTS_USAGE"><choice Name="JTAG (1149.1), SWD and cJTAG are disabled" value="nothing"><property id="SWD Debug" desc="" Type="hiddenfield" Value="disabled" ID="SWD.SWD_DEBUG" /><property id="SWO Data"desc="" Type="hiddenfield" Value="aux_uart" ID="SWD.SWO_DATA" /></choice><choice Name="SWD Mode - Aux COM port is target UART port" value="nothing"><property id="SWD Debug" desc="" Type="hiddenfield" Value="enabled" ID="SWD.SWD_DEBUG" /><property id="SWO Data"desc="" Type="hiddenfield" Value="aux_uart" ID="SWD.SWO_DATA" /></choice><choice Name="SWD Mode - Aux COM port is target TDO pin" value="nothing"><property id="SWD Debug" desc="" Type="hiddenfield" Value="enabled" ID="SWD.SWD_DEBUG" /><property id="SWO Data"desc="" Type="hiddenfield" Value="tdo_pin" ID="SWD.SWO_DATA" /></choice><choice Name="cJTAG (1149.7) 4-pin standard mode" value="enable"><property Name="The Converter Type" Type="hiddenfield" Value="xds110" ID="DOT7.DTS_TYPE" /><property Name="The Debug Probe Clock" Type="hiddenfield" Value="emulator" ID="DOT7.DTS_PROGRAM" /><property Name="The Converter 1149.7 Frequency Value" Type="hiddenfield" Value="1.0MHz" ID="DOT7.DTS_FREQUENCY" /><property Name="The Target Scan Format" Type="hiddenfield" Value="jscan0" ID="DOT7.TS_FORMAT" /><property Name="The Target Pin Width" Type="hiddenfield" Value="all_four" ID="DOT7.TS_PIN_WIDTH" /><property id="SWD Debug" desc="" Type="hiddenfield" Value="disabled" ID="SWD.SWD_DEBUG" /><property id="SWO Data"desc="" Type="hiddenfield" Value="aux_uart" ID="SWD.SWO_DATA" /></choice><choice Name="cJTAG (1149.7) 2-pin advanced modes" value="enable"><property Name="The Converter Type" Type="hiddenfield" Value="xds110" ID="DOT7.DTS_TYPE"/><property Name="The Debug Probe Clock" Type="hiddenfield" Value="emulator" ID="DOT7.DTS_PROGRAM"/><property Name="The Converter 1149.7 Frequency Value" Type="hiddenfield" Value="1.0MHz"ID="DOT7.DTS_FREQUENCY"/><property Name="Target Scan Format" Type="choicelist" Value="1" ID="DOT7.TS_FORMAT"><choice Name="OSCAN1 format - non-adaptive scans" value="oscan1"/><choice Name="OSCAN2 format - faster transitions" value="oscan2"/></property><property Name="The Target Pin Width" Type="hiddenfield" Value="only_two" ID="DOT7.TS_PIN_WIDTH" /><property id="SWD Debug" desc="" Type="hiddenfield" Value="disabled" ID="SWD.SWD_DEBUG" /><property id="XDS110 Aux Port" desc="Auxiliary COM Port Connection" Type="choicelist" Value="0" ID="SWD.SWO_DATA"><choice Name="Aux COM port is target UART port" value="aux_uart" /><choice Name="Aux COM port is target TDO pin" value="tdo_pin" /></property></choice></property>若还是不行的话，请给出相关截图
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user4678620：
谢谢，添加后进入了设置界面，但试了几种设置，都连接不成功，报Error-233，请问如何配置这些参数？
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Susan Yang：
谢谢反馈！我回头确认一下后给您回复
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user4678620：
谢谢，设置为cJTAG-4pin，报Err-230；设置为cJTAG-2pin，报Err-233；设置为JTAG，连接成功。
cJTAG 4PIN-Test Connection.txt
[Start: Texas Instruments XDS100v3 USB Debug Probe_0]Execute the command:%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity[Result]-----[Print the board config pathname(s)]------------------------------------C:\Users\wuqiang.000\AppData\Local\TEXASI~1\CCS\ccs910\0\0\BrdDat\testBoard.dat-----[Print the reset-command software log-file]-----------------------------This utility has selected a 100- or 510-class product. This utility will load the adapter 'jioserdesusbv3.dll'. The library build date was 'Jun3 2019'. The library build time was '15:24:38'. The library package version is '8.2.0.00004'. The library component version is '35.35.0.0'. The controller does not use a programmable FPGA. The controller has a version number of '4' (0x00000004). The controller has an insertion length of '0' (0x00000000). This utility will attempt to reset the controller. This utility has successfully reset the controller.-----[Print the reset-command hardware log-file]-----------------------------The scan-path will be reset by toggling the JTAG TRST signal. The controller is the FTDI FT2232 with USB interface. The link from controller to target is direct (without cable). The software is configured for FTDI FT2232 features. The controller cannot monitor the value on the EMU[0] pin. The controller cannot monitor the value on the EMU[1] pin. The controller cannot control the timing on output pins. The controller cannot control the timing on input pins. The scan-path link-delay has been set to exactly '0' (0x0000).An error occurred while hard opening the controller.-----[An error has occurred and this utility has aborted]--------------------This error is generated by TI's USCIF driver or utilities.The value is '-230' (0xffffff1a). The title is 'SC_ERR_PATH_MEASURE'.The explanation is: The measured lengths of the JTAG IR and DR scan-paths are invalid. This indicates that an error exists in the link-delay or scan-path.[End: Texas Instruments XDS100v3 USB Debug Probe_0]cJTAG 2PIN-Test Connection.txt
[Start: Texas Instruments XDS100v3 USB Debug Probe_0]Execute the command:%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity[Result]-----[Print the board config pathname(s)]------------------------------------C:\Users\wuqiang.000\AppData\Local\TEXASI~1\CCS\ccs910\0\0\BrdDat\testBoard.dat-----[Print the reset-command software log-file]-----------------------------This utility has selected a 100- or 510-class product. This utility will load the adapter 'jioserdesusbv3.dll'. The library build date was 'Jun3 2019'. The library build time was '15:24:38'. The library package version is '8.2.0.00004'. The library component version is '35.35.0.0'. The controller does not use a programmable FPGA. The controller has a version number of '4' (0x00000004). The controller has an insertion length of '0' (0x00000000). This utility will attempt to reset the controller. This utility has successfully reset the controller.-----[Print the reset-command hardware log-file]-----------------------------The scan-path will be reset by toggling the JTAG TRST signal. The controller is the FTDI FT2232 with USB interface. The link from controller to target is direct (without cable). The software is configured for FTDI FT2232 features. The controller cannot monitor the value on the EMU[0] pin. The controller cannot monitor the value on the EMU[1] pin. The controller cannot control the timing on output pins. The controller cannot control the timing on input pins. The scan-path link-delay has been set to exactly '0' (0x0000).An error occurred while hard opening the controller.-----[An error has occurred and this utility has aborted]--------------------This error is generated by TI's USCIF driver or utilities.The value is '-233' (0xffffff17). The title is 'SC_ERR_PATH_BROKEN'.The explanation is: The JTAG IR and DR scan-paths cannot circulate bits, they may be broken. An attempt to scan the JTAG scan-path has failed. The target's JTAG scan-path appears to be broken with a stuck-at-ones or stuck-at-zero fault.[End: Texas Instruments XDS100v3 USB Debug Probe_0]JTAG-Test Connection.txt
[Start: Texas Instruments XDS100v3 USB Debug Probe_0]Execute the command:%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity[Result]-----[Print the board config pathname(s)]------------------------------------C:\Users\wuqiang.000\AppData\Local\TEXASI~1\CCS\ccs910\0\0\BrdDat\testBoard.dat-----[Print the reset-command software log-file]-----------------------------This utility has selected a 100- or 510-class product. This utility will load the adapter 'jioserdesusbv3.dll'. The library build date was 'Jun3 2019'. The library build time was '15:24:38'. The library package version is '8.2.0.00004'. The library component version is '35.35.0.0'. The controller does not use a programmable FPGA. The controller has a version number of '4' (0x00000004). The controller has an insertion length of '0' (0x00000000). This utility will attempt to reset the controller. This utility has successfully reset the controller.-----[Print the reset-command hardware log-file]-----------------------------The scan-path will be reset by toggling the JTAG TRST signal. The controller is the FTDI FT2232 with USB interface. The link from controller to target is direct (without cable). The software is configured for FTDI FT2232 features. The controller cannot monitor the value on the EMU[0] pin. The controller cannot monitor the value on the EMU[1] pin. The controller cannot control the timing on output pins. The controller cannot control the timing on input pins. The scan-path link-delay has been set to exactly '0' (0x0000).-----[The log-file for the JTAG TCLK output generated from the PLL]----------TestSizeCoordMHzFlagResultDescription~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~164- 01 00500.0kHzOgood valuemeasure path length264+ 00 001.000MHz[O]good valueapply explicit tclkThere is no hardware for measuring the JTAG TCLK frequency.In the scan-path tests: The test length was 2048 bits. The JTAG IR length was 6 bits. The JTAG DR length was 1 bits.The IR/DR scan-path tests used 2 frequencies. The IR/DR scan-path tests used 500.0kHz as the initial frequency. The IR/DR scan-path tests used 1.000MHz as the highest frequency. The IR/DR scan-path tests used 1.000MHz as the final frequency.-----[Measure the source and frequency of the final JTAG TCLKR input]--------There is no hardware for measuring the JTAG TCLK frequency.-----[Perform the standard path-length test on the JTAG IR and DR]-----------This path-length test uses blocks of 64 32-bit words.The test for the JTAG IR instruction path-length succeeded. The JTAG IR instruction path-length is 6 bits.The test for the JTAG DR bypass path-length succeeded. The JTAG DR bypass path-length is 1 bits.-----[Perform the Integrity scan-test on the JTAG IR]------------------------This test will use blocks of 64 32-bit words. This test will be applied just once.Do a test using 0xFFFFFFFF. Scan tests: 1, skipped: 0, failed: 0 Do a test using 0x00000000. Scan tests: 2, skipped: 0, failed: 0 Do a test using 0xFE03E0E2. Scan tests: 3, skipped: 0, failed: 0 Do a test using 0x01FC1F1D. Scan tests: 4, skipped: 0, failed: 0 Do a test using 0x5533CCAA. Scan tests: 5, skipped: 0, failed: 0 Do a test using 0xAACC3355. Scan tests: 6, skipped: 0, failed: 0 All of the values were scanned correctly.The JTAG IR Integrity scan-test has succeeded.-----[Perform the Integrity scan-test on the JTAG DR]------------------------This test will use blocks of 64 32-bit words. This test will be applied just once.Do a test using 0xFFFFFFFF. Scan tests: 1, skipped: 0, failed: 0 Do a test using 0x00000000. Scan tests: 2, skipped: 0, failed: 0 Do a test using 0xFE03E0E2. Scan tests: 3, skipped: 0, failed: 0 Do a test using 0x01FC1F1D. Scan tests: 4, skipped: 0, failed: 0 Do a test using 0x5533CCAA. Scan tests: 5, skipped: 0, failed: 0 Do a test using 0xAACC3355. Scan tests: 6, skipped: 0, failed: 0 All of the values were scanned correctly.The JTAG DR Integrity scan-test has succeeded.[End: Texas Instruments XDS100v3 USB Debug Probe_0]
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Susan Yang：
请您给出下面的设置是否可以成功
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user4678620：
目前CCS的设置跟您的图片上是相同的，但是连不上调试器。
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Susan Yang：
您可以在下面的帖子内跟踪回复给出您现在的相关错误截图，请国外的工程师帮忙一起看一下
e2e.ti.com/…/3596458
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user4678620：
问题解决了：
不用更改TIXDS100v3_Dot7_Connection文件内容，此方案不可行；XDS100v3调试器的Advanced 界面支持cJTAG模式选择，在The Converter Usage选项中。
1、若使用TMS和TCK两线制cJTAG模式，在XDS100v3的The Converter Usage下拉菜单中选择Generate 1149.7 2-pin advanced modes
2、若使用TDI、TDO、TMS和TCK四线制cJTAG模式，在XDS100v3的The Converter Usage下拉菜单中选择Generate 1149.7 4-pin standard mode
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Susan Yang：
谢谢您的反馈！我会整理一下放在下一次的FAQ分享
