TI中文支持网自己仿照IWR1642BOOST画的板子，除了仿真机没画其他都一样而且预留了JTAG接口。
我用的是XDS100v3，之前问过100v3也能用。
现在连上仿真器之后程序烧录不进去，但是在CCS中target configuration中的test connection中又显示以下内容：
[Start: Texas Instruments XDS100v3 USB Debug Probe_0]
Execute the command:
%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity
[Result]
—–[Print the board config pathname(s)]————————————
C:\Users\yh\AppData\Local\TEXASI~1\CCS\ti\
0\0\BrdDat\testBoard.dat
—–[Print the reset-command software log-file]—————————–
This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesusbv3.dll'.
The library build date was 'Nov 25 2019'.
The library build time was '16:55:29'.
The library package version is '8.4.0.00006'.
The library component version is '35.35.0.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.
—–[Print the reset-command hardware log-file]—————————–
The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).
—–[The log-file for the JTAG TCLK output generated from the PLL]———-
Test Size Coord MHz Flag Result Description
~~~~ ~~~~ ~~~~~~~ ~~~~~~~~ ~~~~ ~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~
1 64 – 01 00 500.0kHz O good value measure path length
2 64 + 00 00 1.000MHz [O] good value apply explicit tclk
There is no hardware for measuring the JTAG TCLK frequency.
In the scan-path tests:
The test length was 2048 bits.
The JTAG IR length was 4 bits.
The JTAG DR length was 1 bits.
The IR/DR scan-path tests used 2 frequencies.
The IR/DR scan-path tests used 500.0kHz as the initial frequency.
The IR/DR scan-path tests used 1.000MHz as the highest frequency.
The IR/DR scan-path tests used 1.000MHz as the final frequency.
—–[Measure the source and frequency of the final JTAG TCLKR input]——–
There is no hardware for measuring the JTAG TCLK frequency.
—–[Perform the standard path-length test on the JTAG IR and DR]———–
This path-length test uses blocks of 64 32-bit words.
The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 4 bits.
The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.
—–[Perform the Integrity scan-test on the JTAG IR]————————
This test will use blocks of 64 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG IR Integrity scan-test has succeeded.
—–[Perform the Integrity scan-test on the JTAG DR]————————
This test will use blocks of 64 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG DR Integrity scan-test has succeeded.
[End: Texas Instruments XDS100v3 USB Debug Probe_0]
我已经在仿真器型号中更改为了XDS100v3。
我想问的是这些内容是不是能证明仿真器和板子连接成功了？
user6120592：
在通用串行总线控制器这里没有显示XDS100v3 channel A和channel B，不知道是不是因为这个？
但是在这种情况下test connection显示的跟上面一样。
Chris Meng：
user6120592现在连上仿真器之后程序烧录不进去
请问是通过CCS下载代码到芯片内存里报错么？具体错误是什么？在CCS里你成功连接MSS/DSS的核么？
user6120592：
回复 Chris Meng:
我是通过Uniflash烧写程序的。
错误显示为：
Initial response from the device was not received. Please power cycle device before re-flashing.
Not able to connect to serial port. Recheck COM port selected and/or permissions.
CCS上无法连接MSS/DSS的核。
Chris Meng：
回复 user6120592:
你好，
请问2个UART部分，你去掉XDS110的mcu后，是否有外接RS232芯片，转换为两个串口？
user6120592：
回复 Chris Meng:
没有，我只连接了仿真器的JTAG和5V电源和地
user6120592：
回复 Chris Meng:
JTAG我连接了3.3V、TMS、TCK、TDO、TDI和地这六根线
user6120592：
回复 Chris Meng:
又尝试了一下，CCS中我先连MSS再连DSS是可以连接成功的，但是反过来先连DSS就会失败。
MSS和DSS连接成功后加载.xer4f文件时会报错，console显示内容如下：
C674X_0: File Loader: Verification failed: Values at address 0x20000000 do not match Please verify target memory and memory map.
C674X_0: GEL: File: E:\ti_workspace\mmw_dss_16xx\Debug\xwr16xx_mmw_dss.xe674: a data verification error occurred, file load failed.
Cortex_R4_0: Trouble Writing Memory Block at 0x0 on Page 0 of Length 0x3c: (Error -1065 @ 0x0) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 8.4.0.00006)
Cortex_R4_0: File Loader: Verification failed: Target failed to write 0x00000000
Cortex_R4_0: GEL: File: E:\ti_workspace\mmw_mss_16xx\Debug\xwr16xx_mmw_mss.xer4f: Load failed.
Chris Meng：
回复 user6120592:
user6120592没有，我只连接了仿真器的JTAG和5V电源和地
user6120592：
回复 Chris Meng:
是通过RS232烧写程序的？相关引脚有引出，我还以为是通过仿真器烧写的，那仿真器的作用就仅仅是debug吗？烧写程序的时候还用不用连仿真器？还是说仿真器和RS232都要连接？
Chris Meng：
回复 user6120592:
user6120592是通过RS232烧写程序的？
是的。user port的串口来烧写
user6120592那仿真器的作用就仅仅是debug吗？
是的。
在TI毫米波EVM板上，MCU除了实现XDS110 JTAG的功能外，还实现了两路UART转换为usb串口的功能。
