CCS9.1 Erase Settings 问题

Hi：

大家好啊。如图，利用CCS9.1 烧写程序时，设置Flash的擦除区域。当选择图示“Necessary Sectors Only”选项，擦除的FLASH的区域是哪些区域，根据什么来定义擦除区域。谢谢！

Aiden：

回复 Susan Yang:

HI:Susan,能对“Necessary Sections Only: will erase only the Flash regions to which the linker has allocated storage.”这个定义做个细致的讲解吗？
是指CMD文件中的地址分配吗？哪些字段是属于这个定义范围内？
SECTIONS
{codestart: > BEGIN,PAGE = 0, ALIGN(4).text: > APP_FLASH,PAGE = 0, ALIGN(4).cinit: > APP_FLASH,PAGE = 0, ALIGN(4).pinit: > APP_FLASH,PAGE = 0, ALIGN(4).switch: > APP_FLASH,PAGE = 0, ALIGN(4).reset: > RESET,PAGE = 0, TYPE = DSECT /* not used, */
.cio: > RAMLS3,PAGE = 0 .stack: > RAMM0_1,PAGE = 1.ebss: > APP_RAM,PAGE = 1.esysmem: > APP_RAM,PAGE = 1.econst: > APP_FLASH,PAGE = 0, ALIGN(4)
codepattern: > APP_PATTERNPAGE = 0code_crc: > APP_CRCPAGE = 0calpattern: > CAL_PATTERNPAGE = 0cal_crc: > CAL_CRCPAGE = 0
/* ramgs0: > RAMGS0,PAGE = 1 *//* ramgs1: > RAMGS1,PAGE = 1 */
Cla1DataRam: > CLARAM0,PAGE = 1
Cla1Prog:LOAD = APP_FLASH,RUN = RAMLS3,RUN_START(_Cla1funcsRunStart),LOAD_START(_Cla1funcsLoadStart),LOAD_SIZE(_Cla1funcsLoadSize),PAGE = 0, ALIGN(4).const_cla:LOAD = APP_FLASH,RUN = RAMLS4,RUN_START(_Cla1ConstRunStart),LOAD_START(_Cla1ConstLoadStart),LOAD_SIZE(_Cla1ConstLoadSize),PAGE = 0Cla1ToCpuMsgRAM: > CLA1_MSGRAMLOW,PAGE = 1CpuToCla1MsgRAM: > CLA1_MSGRAMHIGH,PAGE = 1ramfuncs: LOAD = APP_FLASH,RUN = RAMLS0_S1_S2,LOAD_START(_RamfuncsLoadStart),LOAD_SIZE(_RamfuncsLoadSize),LOAD_END(_RamfuncsLoadEnd),RUN_START(_RamfuncsRunStart),RUN_SIZE(_RamfuncsRunSize),RUN_END(_RamfuncsRunEnd),PAGE = 0, ALIGN(4)
.scratchpad: > CLARAM0,PAGE = 1.bss_cla: > CLARAM0,PAGE = 1
/* Allocate IQ math areas: */IQmath: > APP_FLASH, PAGE = 0, ALIGN(4)/* Math Code */IQmathTables: > APP_FLASH, PAGE = 0, ALIGN(4)
}

谢谢！

Susan Yang：

回复 Aiden:

将仅擦除 linker 已为其分配存储空间的Flash区域

如下

Aiden.text : > APP_FLASH, PAGE = 0, ALIGN(4) .cinit : > APP_FLASH, PAGE = 0, ALIGN(4) .pinit : > APP_FLASH, PAGE = 0, ALIGN(4) .switch : > APP_FLASH, PAGE = 0, ALIGN(4)

等已经分配存储空间的Flash区域

Aiden：

回复 Susan Yang:

CMD文件中，SECTIONS包含的内容节选如下：
SECTIONS
{
codestart : > BEGIN, PAGE = 0, ALIGN(4)
.text : > APP_FLASH, PAGE = 0, ALIGN(4)
.cinit : > APP_FLASH, PAGE = 0, ALIGN(4)
.pinit : > APP_FLASH, PAGE = 0, ALIGN(4)
.switch : > APP_FLASH, PAGE = 0, ALIGN(4)
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */

.cio : > RAMLS3, PAGE = 0
.stack : > RAMM0_1, PAGE = 1
.ebss : > APP_RAM, PAGE = 1
.esysmem : > APP_RAM, PAGE = 1
.econst : > APP_FLASH, PAGE = 0, ALIGN(4)

/////////////////////////
codepattern : > APP_PATTERN PAGE = 0
code_crc : > APP_CRC PAGE = 0
calpattern : > CAL_PATTERN PAGE = 0
cal_crc : > CAL_CRC PAGE = 0
////////////////////////////////

如你列举
.text : > APP_FLASH, PAGE = 0, ALIGN(4)
.cinit : > APP_FLASH, PAGE = 0, ALIGN(4)
.pinit : > APP_FLASH, PAGE = 0, ALIGN(4)
.switch : > APP_FLASH, PAGE = 0, ALIGN(4)
是已经分配存储空间的Flash区域，
那么这些FLASH区域算不算已经分配的存储空间的FLASH区域？
codepattern : > APP_PATTERN PAGE = 0
code_crc : > APP_CRC PAGE = 0
calpattern : > CAL_PATTERN PAGE = 0
cal_crc : > CAL_CRC PAGE = 0

Susan Yang：

回复 Aiden:

只要是在FLASH的地址里就是已经分配存储空间的Flash区域，这个要看您的APP_PATTERN 等的定义

Aiden：

回复 Susan Yang:

你指的定义是这个吗？

Susan Yang：

回复 Aiden:

是的 linker已经分配内存的

Aiden：

回复 Susan Yang:

但是我发现利用CCS刷新程序时，当选择图示“Necessary Sectors Only”选项。我的APP_FLASH区域是会被擦除并更新，但是APP_PATTERN是不会被擦除的。

Susan Yang：

回复 Aiden:

请问您使用的是哪款芯片呢？若是可以的话，请私信一下您的代码，我来测试一下

Aiden：

回复 Susan Yang:

我使用的是280049，代码是公司电脑，有加密无法发出工程。部分可以拷贝。
具体问题总结一下：1、我在应用程序中制造条件往APP_PATTERN地址（CMD中地址为: origin = 0x08B000, length = 0x001000 /* app pattern @end of application area*/）写入一个标记值（如0x5A5A）.2、当我利用CCS9.1刷新程序时，选择图示“Necessary Sectors Only”选项，应用程序APP_FLASH空间（CMD地址为: origin = 0x082002, length = 0x007FFE /* on-chip Flash, total 44K */）会被擦除更新，因为我的应用程序在不断修改，从功能上能看出来是更新了的。3、CCS9.1更新后程序后，APP_PATTERN地址的数据没有擦除，仿真可以查看到数据还是0x5A5A
CMD完整文件如下：
/*
//###########################################################################
//
// FILE:F28004x.cmd
//
// TITLE:Linker Command File For F28004x Device
//
//###########################################################################
// $TI Release: $
// $Release Date: $
//###########################################################################
*/

MEMORY
{
PAGE 0 :/* BEGIN is used for the "boot to Flash" bootloader mode*/BEGIN: origin = 0x082000, length = 0x000002RAMLS0_S1_S2: origin = 0x008000, length = 0x001800 /*for function running from RAM*/RAMLS3: origin = 0x009800, length = 0x000800 RAMLS4: origin = 0x00A000, length = 0x000800 RESET: origin = 0x3FFFC0, length = 0x000002
APP_FLASH: origin = 0x082002, length = 0x007FFE /* on-chip Flash, total 44K */APP_CRC: origin = 0x08A000, length = 0x001000 /* CRC result of application flash area*/APP_PATTERN: origin = 0x08B000, length = 0x001000 /* app pattern @end of application area*/CAL_FLASH: origin = 0x08C000, length = 0x001000 /* on-chip Flash, total 4K */CAL_CRC: origin = 0x08D000, length = 0x001000 /* CRC result of calibration flash area*/CAL_PATTERN: origin = 0x08E000, length = 0x001000 /* cal pattern @end of calibration area*//*reserved 4k for reflash request at 0x08E000*/EMULATED_EE: origin = 0x08F000, length = 0x001000 /* on-chip Flash, total 4k for EEPROM emulation */
/* BANK 1 */FLASH_BANK1_SEC0: origin = 0x090000, length = 0x001000 /* on-chip Flash */FLASH_BANK1_SEC1: origin = 0x091000, length = 0x001000 /* on-chip Flash */FLASH_BANK1_SEC2: origin = 0x092000, length = 0x001000 /* on-chip Flash */FLASH_BANK1_SEC3: origin = 0x093000, length = 0x001000 /* on-chip Flash */FLASH_BANK1_SEC4: origin = 0x094000, length = 0x001000 /* on-chip Flash */FLASH_BANK1_SEC5: origin = 0x095000, length = 0x001000 /* on-chip Flash */FLASH_BANK1_SEC6: origin = 0x096000, length = 0x001000 /* on-chip Flash */FLASH_BANK1_SEC7: origin = 0x097000, length = 0x001000 /* on-chip Flash */FLASH_BANK1_SEC8: origin = 0x098000, length = 0x001000 /* on-chip Flash */FLASH_BANK1_SEC9: origin = 0x099000, length = 0x001000 /* on-chip Flash */FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000 /* on-chip Flash */FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000 /* on-chip Flash */FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000 /* on-chip Flash */FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000 /* on-chip Flash */FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000 /* on-chip Flash */FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x001000 /* on-chip Flash */

PAGE 1 :

//BOOT_RSVD: origin = 0x000002, length = 0x0000F3/* Part of M0, BOOT rom will use this for stack */
/* RAMM0: origin = 0x0000F5, length = 0x00030B *//* RAMM1: origin = 0x000400, length = 0x000400on-chip RAM block M1 */
RAMM0_1: origin = 0x0000F5, length = 0x00070B
/* RAMLS5: origin = 0x00A800, length = 0x000800 */CLARAM0: origin = 0x00A800, length = 0x000800
CLA1_MSGRAMLOW: origin = 0x001480, length = 0x000080CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080

RAMLS6: origin = 0x00B000, length = 0x000800/*for control loop variables*//* RAMLS7: origin = 0x00B800, length = 0x000800/*for app bss*//* RAMGS0: origin = 0x00C000, length = 0x002000/*for app bss*//* RAMGS1: origin = 0x00E000, length = 0x002000/*for app bss*//* RAMGS2: origin = 0x010000, length = 0x002000/*for app bss*/APP_RAM: origin = 0x00B800, length = 0x006800/*applicaton RAM , total 26K*/
RAMGS3: origin = 0x012000, length = 0x002000 /*for DMA */
}

SECTIONS
{codestart: > BEGIN,PAGE = 0, ALIGN(4).text: > APP_FLASH,PAGE = 0, ALIGN(4).cinit: > APP_FLASH,PAGE = 0, ALIGN(4).pinit: > APP_FLASH,PAGE = 0, ALIGN(4).switch: > APP_FLASH,PAGE = 0, ALIGN(4).reset: > RESET,PAGE = 0, TYPE = DSECT /* not used, */
.cio: > RAMLS3,PAGE = 0 .stack: > RAMM0_1,PAGE = 1.ebss: > APP_RAM,PAGE = 1.esysmem: > APP_RAM,PAGE = 1.econst: > APP_FLASH,PAGE = 0, ALIGN(4)
codepattern: > APP_PATTERNPAGE = 0code_crc: > APP_CRCPAGE = 0calpattern: > CAL_PATTERNPAGE = 0cal_crc: > CAL_CRCPAGE = 0
/* ramgs0: > RAMGS0,PAGE = 1 *//* ramgs1: > RAMGS1,PAGE = 1 */
Cla1DataRam: > CLARAM0,PAGE = 1
Cla1Prog:LOAD = APP_FLASH,RUN = RAMLS3,RUN_START(_Cla1funcsRunStart),LOAD_START(_Cla1funcsLoadStart),LOAD_SIZE(_Cla1funcsLoadSize),PAGE = 0, ALIGN(4).const_cla:LOAD = APP_FLASH,RUN = RAMLS4,RUN_START(_Cla1ConstRunStart),LOAD_START(_Cla1ConstLoadStart),LOAD_SIZE(_Cla1ConstLoadSize),PAGE = 0Cla1ToCpuMsgRAM: > CLA1_MSGRAMLOW,PAGE = 1CpuToCla1MsgRAM: > CLA1_MSGRAMHIGH,PAGE = 1ramfuncs: LOAD = APP_FLASH,RUN = RAMLS0_S1_S2,LOAD_START(_RamfuncsLoadStart),LOAD_SIZE(_RamfuncsLoadSize),LOAD_END(_RamfuncsLoadEnd),RUN_START(_RamfuncsRunStart),RUN_SIZE(_RamfuncsRunSize),RUN_END(_RamfuncsRunEnd),PAGE = 0, ALIGN(4)
.scratchpad: > CLARAM0,PAGE = 1.bss_cla: > CLARAM0,PAGE = 1
/* Allocate IQ math areas: */IQmath: > APP_FLASH, PAGE = 0, ALIGN(4)/* Math Code */IQmathTables: > APP_FLASH, PAGE = 0, ALIGN(4)
}

SECTIONS
{/*************DPLIB Sections C28x************************/CAL_01_Section: > CAL_FLASHPAGE = 0
CAL_02_Section: > CAL_FLASHPAGE = 0
CAL_03_Section: > CAL_FLASHPAGE = 0CAL_04_Section: > CAL_FLASHPAGE = 0
CAL_05_Section: > CAL_FLASHPAGE = 0
CAL_06_Section: > CAL_FLASHPAGE = 0CAL_07_Section: > CAL_FLASHPAGE = 0
CAL_08_Section: > CAL_FLASHPAGE = 0
CAL_09_Section: > CAL_FLASHPAGE = 0CAL_10_Section: > CAL_FLASHPAGE = 0
CAL_11_Section: > CAL_FLASHPAGE = 0
CAL_12_Section: > CAL_FLASHPAGE = 0CAL_13_Section: > CAL_FLASHPAGE = 0
CAL_14_Section: > CAL_FLASHPAGE = 0
CAL_15_Section: > CAL_FLASHPAGE = 0CAL_16_Section: > CAL_FLASHPAGE = 0
CAL_17_Section: > CAL_FLASHPAGE = 0
CAL_18_Section: > CAL_FLASHPAGE = 0CAL_19_Section: > CAL_FLASHPAGE = 0
CAL_20_Section: > CAL_FLASHPAGE = 0
CAL_21_Section: > CAL_FLASHPAGE = 0CAL_22_Section: > CAL_FLASHPAGE = 0
CAL_23_Section: > CAL_FLASHPAGE = 0CAL_24_Section: > CAL_FLASHPAGE = 0
CAL_25_Section: > CAL_FLASHPAGE = 0CAL_26_Section: > CAL_FLASHPAGE = 0CAL_27_Section: > CAL_FLASHPAGE = 0CAL_28_Section: > CAL_FLASHPAGE = 0CAL_29_Section: > CAL_FLASHPAGE = 0CAL_30_Section: > CAL_FLASHPAGE = 0CAL_31_Section: > CAL_FLASHPAGE = 0CAL_32_Section: > CAL_FLASHPAGE = 0CAL_33_Section: > CAL_FLASHPAGE = 0

}

SECTIONS
{
/*************DPLIB Sections C28x************************//* ADCDRV_1ch section */ADCDRV_1ch_Section: > RAMLS6PAGE = 1
/* ADCDRV_4ch section */ADCDRV_4ch_Section: > RAMLS6PAGE = 1
/* ADCDRV_8ch section */ADCDRV_8ch_Section: > RAMLS6PAGE = 1
/* CNTL_2P2Z section */CNTL_2P2Z_Section: > RAMLS6PAGE = 1CNTL_2P2Z_InternalData: > RAMLS6PAGE = 1CNTL_2P2Z_Coef: > RAMLS6PAGE = 1
/* CNTL_3P3Z section */CNTL_3P3Z_Section: > RAMLS6PAGE = 1CNTL_3P3Z_InternalData: > RAMLS6PAGE = 1CNTL_3P3Z_Coef: > RAMLS6PAGE = 1
/*DLOG_4CH section */DLOG_4CH_Section: > RAMLS6PAGE = 1DLOG_BUFF: > RAMLS6PAGE = 1
/*MATH_EMAVG section */MATH_EMAVG_Section: > RAMLS6PAGE = 1
/*PFC_ICMD section*/PFC_ICMD_Section: > RAMLS6PAGE = 1
/*PFC_INVSQR section*/PFC_INVSQR_Section: > RAMLS6PAGE = 1
/* DACDRV_RAMP section */DACDRV_RAMP_Section: > RAMLS6PAGE = 1
/* PWMDRV_1ch driver section */PWMDRV_1ch_Section: > RAMLS6PAGE = 1
/* PWMDRV_1chHiRes driver section */PWMDRV_1chHiRes_Section: > RAMLS6PAGE = 1
/* PWMDRV_PFC2PhiL driver section */PWMDRV_PFC2PhiL_Section: > RAMLS6PAGE = 1
/* PWMDRV_PSFB driver section */PWMDRV_PSFB_Section: > RAMLS6PAGE = 1
/* PWMDRV_DualUpDwnCnt driver section */PWMDRV_DualUpDwnCnt_Section: > RAMLS6PAGE = 1
/* PWMDRV_ComplPairDB driver section */PWMDRV_ComplPairDB_Section: > RAMLS6PAGE = 1
/* ZeroNet_Section*/ZeroNet_Section: > RAMLS6PAGE = 1
/* Net_terminals_Section*/Net_terminals: > RAMLS6PAGE = 1
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/