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因为BOOT方式为PCIE，所以PCIE相关初始化应该在BOOTLOADER中已经实现。如下代码是我对PCIE相关配置，但是无法在WINDOWS下补货MSI中断。不知道配置那里有问题。
#include <stdio.h>
#include <stdint.h>
#include <ti/csl/cslr_pcie_cfg_space_endpoint.h>
#include <ti/csl/cslr_pcie_cfg_space_rootcomplex.h>
#include <ti/csl/cslr_pciess_app.h>
#include <ti/csl/cslr_device.h>
#include <ti/csl/csl_serdes_pcie.h>
#include <ti/csl/csl_pscAux.h>
#include <ti/csl/csl_bootcfgAux.h>
#include <ti/csl/cslr_pciess_cfgtype0.h>
#include <ti/csl/cslr_pciess_cfgtype1.h>
#include <ti/csl/csl_chip.h>
#include <ti/csl/cslr_device.h>
#include <ti/csl/tistdtypes.h>
#include <ti/csl/csl_serdes.h>
#include <c6x.h>
#include <ti/csl/csl_device_interrupt.h>
#include <ti/csl/csl_edma3.h>
#include <ti/csl/CSL_msmc.h>
#include <ti/csl/CSL_msmcAux.h>
#include <ti/csl/cslr_cgem.h>
#include <ti/csl/csl_cgemAux.h>
#include <ti/csl/cslr_xmc.h>
#include <ti/csl/csl_xmcAux.h>
#include <ti/csl/cslr_gpio.h>
#include <ti/csl/cslr_cpintc.h>
#include <ti/csl/csl_gpio.h>
#include <ti/csl/tistdtypes.h>
#include <ti/csl/cslr_pllc.h>
#include <ti/csl/cslr_bootcfg.h>
#include <ti/csl/cslr_tpcc.h>
#include <ti/csl/cslr_tptc.h>
#include <ti/csl/cslr_tmr.h>
#include <ti/csl/cslr_vusr.h>
#include <ti/csl/csl_psc.h>
#include <ti/csl/csl_cache.h>
#include <ti/csl/csl_cacheAux.h>
#include <ti/csl/csl_idma.h>
#include <ti/csl/cslr_mpu.h>
#include <ti/csl/cslr_emif4f.h>
#include <ti/csl/cslr_tetris_vbusp.h>
#include <ti/sysbios/family/c64p/Hwi.h>
CSL_CPINTCRegs* gpCIC1_regs = (CSL_CPINTCRegs*)CSL_CIC_1_REGS;
/*The register pointer for the CIC routing events CPU.
By default, it is CIC0; but for core 4~7, it is CIC1*/
CSL_CPINTCRegs* gpCIC_regs= (CSL_CPINTCRegs*)CSL_CIC_0_REGS;
CSL_CPINTCRegs* gpCIC0_regs = (CSL_CPINTCRegs*)CSL_CIC_0_REGS;
CSL_CgemRegs * gpCGEM_regs = (CSL_CgemRegs *)CSL_C66X_COREPAC_REG_BASE_ADDRESS_REGS;
static inline unsigned int SWAP_ENDIAN(unsigned int byte_index)
{
//此处需要注意
#ifdef _BIG_ENDIAN
return ((byte_index&0xFFFFFFFC)+(3-byte_index&3));
#else
return byte_index;
#endif
}
/*enable interrupt to CPU: IER |= uiIER_en_mask; GIE=1*/
void CPU_interrupt_enable(Uint32 uiIER_en_mask)
{
IER |= uiIER_en_mask;
//enable GIE
TSR = TSR|1;
}
static inline void KeyStone_CIC_event_map(CSL_CPINTCRegs* cpIntcRegs,int input_event_num, int out_num)
{
/*Map input event to output*/
cpIntcRegs->CH_MAP[SWAP_ENDIAN(input_event_num)]= out_num;
/*clear input interrupts events*/
cpIntcRegs->STATUS_CLR_INDEX_REG= input_event_num;
/*enable input interrupts events*/
cpIntcRegs->ENABLE_SET_INDEX_REG= input_event_num;
/*enable output*/
cpIntcRegs->HINT_ENABLE_SET_INDEX_REG= out_num;
}
int uiPCIE_error_host_event_num=0;
int uiPCIE_MSI_host_event_num=1;
void PCIE_Interrupts_Init(void)
{
/* Disable Global host interrupts. */
gpCIC0_regs->GLOBAL_ENABLE_HINT_REG= 0;
/*map PCIE error/PM/RESET Interrupt events to CIC0 out0*/
//PCIE的普通事件中断
KeyStone_CIC_event_map(gpCIC0_regs, CSL_CIC0_PCIE_INT12, uiPCIE_error_host_event_num);
KeyStone_CIC_event_map(gpCIC0_regs, CSL_CIC0_PCIE_INT13, uiPCIE_error_host_event_num);
/* Enable Global host interrupts. */
gpCIC0_regs->GLOBAL_ENABLE_HINT_REG= 1;
/*map PCIE error/PM/RESET interrupt form CICO to INT5;
map PCIE MSI interrupt to INT4*/
//PCIE的MIS事件中断
gpCGEM_regs->INTMUX1 = (CSL_C66X_COREPAC_CIC_OUT0<<CSL_CGEM_INTMUX1_INTSEL5_SHIFT)
|(CSL_C66X_COREPAC_PCIE_INT4_PLUS_N<<CSL_CGEM_INTMUX1_INTSEL4_SHIFT)
|(CSL_C66X_COREPAC_CIC_OUT1<<CSL_CGEM_INTMUX1_INTSEL6_SHIFT);
//enable INT4~INT6
CPU_interrupt_enable((1<<4)|(1<<5)|(1<<6));
}
int main(viod)
{
PCIE_Interrupts_Init();
*(unsigned int*)0x21800200 = 0xF7100001;//RC bar0 addr 0xF7100000 outband OB_OFFSET_INDEX
*(unsigned int*)(0x21800204) = 0x00;//OB_OFFSET_HI
*(unsigned int*)0x21801050=0x417050;//MSI_CAP
*(unsigned int*)0x21801054=0xF7100054;//MSI_LOW32
*(unsigned int*)0x21801058=0x00;//MSI_UP32
*(unsigned int*)0x2180105c=16;//MSI_DATA
puts("PCIE test msi start.");
*(unsigned int*)(0x50000108)=0xf;//MSI_IRQ_ENABLE_SET
*(unsigned int*)(0x50000054) =16;//MSI_IRQ
*(unsigned int*)(0x5000010C)=0xf;//MSI_IRQ_ENABLE_CLR
puts("PCIE test msi end.");
}
使用WINDOWS查PCIE的 BAR0地址为 0xF7100000 windows下捕获不到MSI中断。不知道配置那里存在问题
Shine：
请看一下MSI_IRQ_STATUS 状态位有没有发生改变？
user5315971：
回复 Shine:
你好是MSI0_IRQ_STATUS寄存器吗， Each bit indicates status of MSI vector (24, 16, 8, 0) associated with the bit. Each of the bits can be written with 1 to clear the respective interrupt status bit.我没明白0,8,16,24）代表什么意思
Shine：
回复 user5315971:
MSI中断可以有32个events事件来产生。这32个events是通过往MSI_IRQ寄存器写MSI vector矢量值来触发的。
通过查看MSI0_IRQ_STATUS的标志位可以判断中断有没有发生。
user5315971：
回复 Shine:
有一下几个问题没有明白：第一个问题，直接用仿真器在CCS窗口写0x21800108写0xF,然后写0x21800054寄存器，写8,MSI0_IRQ_STATUS的值会是2。
第二个问题，OUTBAND地址映射，我在DSP的0x21801010地址看到BAR0地址为0xF7100000,通过outband映射将其0xF7100001写入0x21800200地址，此处我不明白写0x50000000开始的偏移地址是多少，看参考代码直接偏移0x54,可是我写0x50000054,如法使得MSI0_IRQ_STATUS状态发生改变。此处应该怎么算偏移
Shine：
回复 user5315971:
建议您到e2e上咨询一下，有专门的产品线工程师解答。
e2e.ti.com/…/791
