TI中文支持网这段时间在用3007，我只是想用它的内部音效处理器对MIC输入的声音做音效处理，而不需要输出到I2S总线上。我现在遇到了两个问题，请教各位
1、是否可以关闭I2S的时钟？因为使用不带I2S接口的MCU可以降低好多成本。
2、从信号通路上看，请看附件，如果不走I2S通道，那么它的信号必须通过SW-D1才能通过给后面的音效处理单元，但是如果不是用I2S通道而使用SW-D1，那只有在record-only模式下才行，这个时候输出DAC又是power down的。
以上两个问题，搞的我很矛盾，请教各位，谢谢
user151383853：
The audio bus of the TLV320AIC3007 can be configured for left or right justified, I2S, DSP, or TDM modes of operation, where communication with standard telephony PCM interfaces is supported within the TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In addition, the word clock (WCLK or GPIO1) and bit clock (BCLK) can be independently configured in either Master or Slave mode, for flexible connectivity to a wide variety of processorsThe word clock (WCLK or GPIO1) is used to define the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC and DAC sampling frequencies.The bit clock (BCLK) is used to clock in and out the digital audio data across the serial bus. When in Master mode, this signal can be programmed in two further modes: continuous transfer mode, and 256-clock mode. In continuous transfer mode, only the minimal number of bit clocks needed to transfer the audio data are generated, so in general the number of bit clocks per frame will be two times the data width. For example, if data width is chosen as 16-bits, then 32 bit clocks will be generated per frame. If the bit clock signal in master mode will be used by a PLL in another device, it is recommended that the 16-bit or 32-bit data width selections be used. These cases result in a low jitter bit clock signal being generated, having frequencies of 32 × Fs or 64 × Fs. In the cases of 20-bit and 24-bit data width in master mode, the bit clocks generated in each frame will not all be of equal period, due to the device not having a clean 40 × Fs or 48 × Fs clock signal readily available. The average frequency of the bit clock signal is still accurate in these cases (being 40 × Fs or 48 × Fs), but the resulting clock signal has higher jitter than in the 16-bit and 32-bit cases.In 256-clock mode, a constant 256 bit clocks per frame are generated, independent of the data width chosen. The TLV320AIC3007 further includes programmability to 3-state the DOUT line during all bit clocks when valid data is not being sent. By combining this capability with the ability to program at what bit clock in a frame the audio data will begin, time-division multiplexing (TDM) can be accomplished, resulting in multiple codecs able to use a single audio serial data bus.
这个通信信号里的时钟还有特别的用途, 看这里还不能轻易地取消掉
