TI中文支持网根据数据手册4.2的配置，寄存器都配置正确，但HPL和HPR没有输出
Stereo DAC Playback with 48ksps Sample Rate and Low Power Mode
Assumption: MCLK = 12.288MHz, Slave I2S
#———– Initialize to page 0
w 30 00 00
#———– Initialize the device through software reset
w 30 01 01
#———– Power up the NDAC divide with value 1
w 30 0b 81
#———– Power up the MDAC divider with value 4
w 30 0c 84
#———– Program the OSR of DAC to 64
w 30 0d 00
w 30 0e 40
#———– Set the DAC mode to PRB_P8
w 30 3c 08
#———– Select page 1
w 30 00 01
#———– Disable internal crude AVdd in presence of external AVdd supply
#———– or before powering up internal AVdd LDO
w 30 01 08
#———– Enable master analog power control
w 30 02 00
#———– Set the REF charging time to 40ms
w 30 7b 01
#———– Set the input common mode to 0.9V and output common mode for headphone
#———– to input common mode
w 30 0a 00
#———– Route left DAC to HPL
w 30 0c 08
#———– Route right DAC to HPR
w 30 0d 08
#———– Set the DAC PTM mode to PTM_P1
w 30 03 08
w 30 04 08
#———– Set the HPL gain to 0dB
w 30 10 00
#———– Set the HPR gain to 0dB
w 30 11 00
#———– HP soft stepping settings for optimal pop performance at power up
#———– Rpop used is 6k with N = 6 & soft step = 20usec.
w 30 14 29
#———– Power up HPL and HPR drivers
w 30 09 30
#———– Wait for 2.5 sec for soft stepping to take effect
#———– Else read Page 1, Register 63d, D(7:6). When = “11” soft-stepping is complete
#———– Select page 0
w 30 00 00
#———– Power up the left and right DAC channels and route the left channel I2S data
#———– to left channel DAC and right channel I2S data to right channel DAC
w 30 3f d4
#———– Unmute the DAC digital volume control
w 30 40 00
user5142806：
补充：STM32F4作为I2S主机发送数据，MCLK=12.288MHZ,WCLK=48K.
