TI中文支持网配置如下：
/* DAC Step */
{0x00, 0x00}, //Select Page 0
{0x0b, 0x81}, //NDAC = 1,Power up
{0x0c, 0x88}, //MDAC = 8,Power up
{0x0d, 0x01}, //DOSR = 128
{0x0e, 0x00}, //DOSR LSB
//{0x3c, 0x02}, //PRB_P2
{0x3c, 0x01},
//{0x43, 0x80},//enable Headset Detection
//{0x35, 0x02},
/* ADC Step */
{0x12, 0x81}, //NADC = 1,Power up
{0x13, 0x90}, //MADC = 8,Power up
{0x14, 0x80}, //AOSR = 128
//{0x3d, 0x01}, //PRB_R1
{0x3d, 0x02}, //PRB_R1
{0x1D, 0x03},//BDIV_CLKIN = ADC_MOD_CLK
{0x1E, 0x82},//BCLK N divider powered up,BCLK N divider = 2.
/* Audio Interface */
{0x1b, 0x0C}, //I2s,16bit,bclk,wclk output from device
{0x55, 0x00}, //ADC Phase Adjust Register
/* Power Step */
{0x00, 0x01}, //Select Page 1
{0x01, 0x08}, //Disabled weak connection of AVDD with DVDD
{0x02, 0x01}, //Analog Block Power up,AVDD LDO Power up
//{0x0a,0x3b}, //Input Vcom = 0.9v,Output Vcom = 1.65v
{0x0a, 0x03},
{0x03, 0x00}, //DAC PTM mode to PTM_P3/4
{0x04, 0x00},
{0x3d, 0x00}, //ADC PTM mode to PTM_R4
// {0x7b,0x01}, //REF settime to 40ms
// {0x14,0x25}, //HP settime to
/* Input Step */
//{0x34, 0x10}, //Route IN2L to LEFT_P with 10k
//{0x36, 0x10}, //Route IN2R to LEFT_M with 10k
{0x34, 0x04}, //Route IN3L to LEFT_P with 10k
//{0x36, 0x40}, //Route CM to LEFT_M with 10k
{0x36, 0x04},
{0x37, 0x04}, //Route IN3R to RIGHT_P with 10k
{0x39, 0x04}, //Route IN3L to RIGHT_M with 10k
//{0x3A,0x04},// IN3R input is weakly driven to common mode.
{0x3b, 0x50}, //Left MicPGA not mute,gain to 28dB
{0x3c, 0x50}, //Right MicPGA not mute,gain to 28dB
//{0x33, 0x68}, //MICBIAS 2.5v, LDOIN
{0x33, 0x40}, /* Output Step */
{0x0c, 0x08}, //Route Left DAC to HPL
//{0x0c, 0x0A}, //Route Left DAC ,MAL to HPL
{0x0d, 0x10}, //Route Left DAC to HPR
//{0x0d, 0x12}, //Route Left DAC \MAR to HPR
{0x10, 0x08}, //HPL gain to 11dB
{0x11, 0x08}, //HPR gain to 11dB
{0x16, 0x75}, //IN1L to HPL, MUTE
{0x17, 0x75}, //IN1R to HPR, MUTE
//{0x16, 0x00}, //IN1L to HPL,-10db
//{0x17, 0x00},//IN1R to HPR, -10db
{0x18, 0x00},//Mixer Amplifier Left Volume -0
{0x19, 0x00},//Mixer Amplifier Right Volume -0
//{0x09, 0x3c}, //LOL,LOR,HPL,HPR,Power up
//{0x09, 0x33}, //MAL,MAR,HPL,HPR,Power up
{0x09, 0x30}, //HPL,HPR,Power up
/* Initial ok */
{0x00, 0x00}, //Select Page 0
{0x3f, 0xd6}, //L&R DAC Power up
{0x40, 0x00}, //L&R DAC not mute
{0x51, 0xc0}, //L&R ADC Power up
{0x52, 0x00}, //L&R ADC not mute, ADC Fine Gain Adjust
{0x53, 0x00}, //Left ADC Digital gain
{0x54, 0x00}, //Right ADC Digital gain
longxinag liu：
请问是什么问题？
Kailyn Chen：
回复 longxinag liu:
差分输入，每个输入端的幅值范围是多少？ 方便附上电路图吗，看下输入端电路。
longxinag liu：
回复 Kailyn Chen:
幅值范围要求多少？ 原理图见附件。
