要实现:
1.事件触发并且进入TZ中断服务函数执行,并且下次触发到来还能再次触发TZ中断;
2.上电强制将PWM1A/PWM1B拉高(由于PWM加了反向),使用mPWM1_OFF()必定会导致触发TZ中断,有没有什么方法能避免该情况?
3.能直接操作TZFLG标志位吗,如下代码,我试了一下怎么没有效果啊?
EALLOW;
EPwm1Regs.TZFLG.all = 0x0005;
EDIS;
代码如下:
#define mPWM1_ON() { EALLOW; \
EPwm1Regs.TZCLR.bit.OST = 1; \
EDIS;}
#define mPWM1_OFF() { EALLOW; \
EPwm1Regs.TZFRC.bit.OST = 1; \
EDIS; }
void InitEPwm1Example()
{
// Enable TZ1 and TZ2 as one shot trip sources
EALLOW;
EPwm1Regs.TZSEL.bit.OSHT1 = 1;
EPwm1Regs.TZSEL.bit.OSHT2 = 0;
// What do we want the TZ1 and TZ2 to do?
EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_HI;//在捕获事件时,ePWM1A被强制拉高
EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
// Enable TZ interrupt
EPwm1Regs.TZEINT.bit.OST = 1;
EDIS;
EPwm1Regs.TBPRD = 6000; // Set timer period
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV4;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare EPwm1Regs.CMPA.half.CMPA = 3000;
// Set actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
EPwm1Regs.AQCTLB.bit.CAD = AQ_SET;
mPWM1_OFF();
}
囧:
TZ的标志清楚需要使用TZCLR寄存器来清楚,不能直接写TZFLG是无效的。 可以尝试使用AQ模块中的AOFS寄存器,也可以强制控制PWM电平,但是他在DB模块前面,注意DB的反向影响。