TI中文支持网Hi TI
Regarding of TPS51220A specification page25 has a note “ if the user wants a further reduction of jitter, using the external clock synchronization provides adjustable phase shift between channels to avoid overlapping of switching events. See the PWM Frequency Control section.“
*this part only support 200kHz – 1MHz operation.
Is there any other way to improve the jitter issue? Can I change the frequency to 165Khz that jitter result is pass? it's whether it violates the guide?
Or, Does TI have a jitter limit that defines TPS51220A in various vin conditions?
Condition :
Vin = 8vin & 13.5vin & 17vin
Fsw=332Khz
Vout=1.8
Johnsin Tao：
Hi造成问题的也可能是你layout。
chan leo：
回复 Johnsin Tao:
hi Johnsin : SPEC page28 note : IOCL(PEAK)=VOCL/RSENSE reason : request to updated next version of the loading becomes larger (13.2Amax change to 13.68Amax), so it changed R-sense part value, and it's form 4mohm change to 2.5mohm or 3mohm.
*The R-sense part value is changed to smaller, the jitter waveform is larger Iout test 4loads : 0%(0A), 25%(3.42A), 75%(6.84A), 100%(13.68A) Does TI have a jitter limit that defines TPS51220A in various vin conditions? when 332khz : jitter all fail when 165khz : jitter all pass
waveform as follow,
TPS51220A-Q1_P1V8_pretest.7z
I want to ask : the previous version and the new layout have not been modified, only change the R-sense part value and the Iout(load) value in the circuit diagram. This action affects the "Voltage feedback ramp signal" which is greater than 30mv (page32).
In addition to the attempt to change the frequency mentioned in the SPEC, are there any other parts parameters that can be adjusted?
