TI中文支持网配置代码如下：
void InitEPwm1Example()
{
EPwm1Regs.TBPRD = 300; // Set timer period
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;
// Setup compare
EPwm1Regs.CMPA.half.CMPA = 100;
// Set actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on CAU
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on CAD
EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Clear PWM1B on CAU
EPwm1Regs.AQCTLB.bit.CAD = AQ_SET; // Set PWM1B on CAD
EALLOW;
EPwm1Regs.HRCNFG.all = 0x0;
EPwm1Regs.HRCNFG.bit.EDGMODE = HR_BEP; // MEP control on both edges
EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP; // CMPAHR and TBPRDHR HR control
EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO_PRD; // load on CTR = 0 and CTR = TBPRD
EPwm1Regs.HRCNFG.bit.AUTOCONV = 1; // Enable autoconversion for HR period
EPwm1Regs.HRPCTL.bit.TBPHSHRLOADE = 1; // Enable TBPHSHR sync (required for updwn count HR control)
EPwm1Regs.HRPCTL.bit.HRPE = 1; // Turn on high-resolution period control.
EDIS;
EPwm1Regs.TBCTL.bit.PHSEN = 1;
EPwm1Regs.TBPRDHR = 32 << 8;
EPwm1Regs.CMPA.half.CMPAHR = 16 << 8;
// Interrupt where we will change the Deadband
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_PRDZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 3rd event
}
void InitEPwm2Example()
{
EPwm2Regs.TBPRD = 300; // Set timer period
EPwm2Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCLK
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow just to observe on the scope
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;
// Setup compare
EPwm2Regs.CMPA.half.CMPA = 150;
// Set actions
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on CAU
EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM2A on CAD
EPwm2Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Clear PWM2B on CAU
EPwm2Regs.AQCTLB.bit.CAD = AQ_SET; // Set PWM2B on CAD
// Active Low complementary PWMs – setup the deadband
// EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
// EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC;
// EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
// EPwm2Regs.DBRED = EPWM2_MIN_DB;
// EPwm2Regs.DBFED = EPWM2_MIN_DB;
// EPwm2_DB_Direction = DB_UP;
EALLOW;
EPwm2Regs.HRCNFG.all = 0x0;
EPwm2Regs.HRCNFG.bit.EDGMODE = HR_BEP; // MEP control on both edges
EPwm2Regs.HRCNFG.bit.CTLMODE = HR_CMP; // CMPAHR and TBPRDHR HR control
EPwm2Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO_PRD; // load on CTR = 0 and CTR = TBPRD
EPwm2Regs.HRCNFG.bit.AUTOCONV = 1; // Enable autoconversion for HR period
EPwm2Regs.HRPCTL.bit.TBPHSHRLOADE = 1; // Enable TBPHSHR sync (required for updwn count HR control)
EPwm2Regs.HRPCTL.bit.HRPE = 1; // Turn on high-resolution period control.
EDIS;
EPwm2Regs.TBCTL.bit.PHSEN = 1;
EPwm2Regs.TBPRDHR = 32 << 8;
EPwm2Regs.CMPA.half.CMPAHR = 16 << 8;
// Interrupt where we will modify the deadband
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_PRDZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 3rd event
}
其中EPWM1和EPWM2都使能了高精度调宽和调频，采用EPWM1的ZRO和PRD事件触发进入中断，在中断中改变EPWM1的CMPA值，使得
能够产生所需波形，但事实上产生只有120这个值被置入，中断代码如下：
#pragma CODE_SECTION(epwm1_isr, "ramfuncs");
__interrupt void epwm1_isr(void)
{
if(EPwm1Regs.TBSTS.bit.CTRDIR == 1 )
{
EPwm1Regs.CMPA.half.CMPA = 150;
}
else
{
EPwm1Regs.CMPA.half.CMPA = 120;
}
//GpioDataRegs.GPATOGGLE.bit.GPIO0 = 1;
// Clear INT flag for this timer
EPwm1Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
实测中断频率正确，但是下降沿出现的位置不对，即150置入没有生效，只能产生与120比较的事件进而导致电平翻转，
但在不使能高精度时，下降沿出现的位置正确，求教：是否在使用高精度时，EPWM不支持双缓冲刷新？
Annie Liu：
为更加有效地解决您的问题，我们建议您将问题发布在E2E英文技术论坛上https://e2e.ti.com/support/microcontrollers/c2000/f/171，将由资深的工程师为您提供帮助。我们的E2E英文社区有TI专家进行回复，并得到全球各地工程师的支持，分享他们的知识和经验。
