TI中文支持网各位先進前輩大家好!
我有一個F28075晶片無法燒入程式的問題想要在這裡請教
首先我參照可以正常運作的F28035電路圖與F2837x controlCARD的設計圖去設計我的F28075電路，
在電路完成後我先嘗試
測試JTAG connection結果如下
[Start: Texas Instruments XDS100v2 USB Debug Probe_0]
Execute the command:
%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity
[Result]
—–[Print the board config pathname(s)]————————————
C:\Users\Don_Liu\AppData\Local\TEXASI~1\
CCS\ti\3\0\BrdDat\testBoard.dat
—–[Print the reset-command software log-file]—————————–
This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesusb.dll'.
The library build date was 'Jul 21 2017'.
The library build time was '19:36:41'.
The library package version is '7.0.48.0'.
The library component version is '35.35.0.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.
—–[Print the reset-command hardware log-file]—————————–
The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).
—–[The log-file for the JTAG TCLK output generated from the PLL]———-
There is no hardware for programming the JTAG TCLK frequency.
—–[Measure the source and frequency of the final JTAG TCLKR input]——–
There is no hardware for measuring the JTAG TCLK frequency.
—–[Perform the standard path-length test on the JTAG IR and DR]———–
This path-length test uses blocks of 64 32-bit words.
The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 6 bits.
The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.
—–[Perform the Integrity scan-test on the JTAG IR]————————
This test will use blocks of 64 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG IR Integrity scan-test has succeeded.
—–[Perform the Integrity scan-test on the JTAG DR]————————
This test will use blocks of 64 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG DR Integrity scan-test has succeeded.
[End: Texas Instruments XDS100v2 USB Debug Probe_0]
但我按下debug燒入後卻一直重複出現以下兩個問題
C28xx_CPU1: Error connecting to the target: (Error -1135 @ 0x0) The debug probe reported an error. Confirm debug probe configuration and connections, reset the debug probe, and retry the operation. (Emulation package 7.0.48.0)
C28xx_CPU1: Error connecting to the target: (Error -1015 @ 0x0) Device is not responding to the request. Device may be locked, or the debug probe connection may be unreliable. Unlock the device if possible (e.g. use wait in reset mode, and power-cycle the board). If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 7.0.48.0)
期間我嘗試過以下的量測：
1. 查看晶片的所有VDDIO與GND是否有正確接上，量測結果都有。
2. 更換過另外兩塊相同電路去燒入也出現一樣的失敗。
3.查看nRXS pin也是都有出現250usec low / 27.5msec high的訊號。
4. 查看TMS、TDI、TDO、nReset與TCK pin都看到燒入的初期有訊號交握，且所有pin的訊號都沒有失真。
5. 嘗試將VREGENZ pin pull high，並在所有VDD pin上外加1.2V，結果還是無法燒入。
6. 確認72與84 pin都是pull high讓晶片work在Get Mode。
7. 嘗試更換新的晶片也出現一樣的失敗。
8. 將我的JTAG燒入器拿去燒入F28035程式至F28035晶片結果可以(這樣看來我燒入器應該是沒問題的)
9. 嘗試用Uniflash燒入也一樣沒用。
請問我還有什麼沒有注意到或什麼狀況會導致跟我一樣的問題的嗎???
謝謝您們的關注
Don-Liu
mangui zhang：测试一下clkout管脚是否有输出波形确保硬件没有问题
还有确认一下芯片来源感觉像是被lock了
各位先進前輩大家好!
我有一個F28075晶片無法燒入程式的問題想要在這裡請教
首先我參照可以正常運作的F28035電路圖與F2837x controlCARD的設計圖去設計我的F28075電路，
在電路完成後我先嘗試
測試JTAG connection結果如下
[Start: Texas Instruments XDS100v2 USB Debug Probe_0]
Execute the command:
%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity
[Result]
—–[Print the board config pathname(s)]————————————
C:\Users\Don_Liu\AppData\Local\TEXASI~1\
CCS\ti\3\0\BrdDat\testBoard.dat
—–[Print the reset-command software log-file]—————————–
This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesusb.dll'.
The library build date was 'Jul 21 2017'.
The library build time was '19:36:41'.
The library package version is '7.0.48.0'.
The library component version is '35.35.0.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.
—–[Print the reset-command hardware log-file]—————————–
The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).
—–[The log-file for the JTAG TCLK output generated from the PLL]———-
There is no hardware for programming the JTAG TCLK frequency.
—–[Measure the source and frequency of the final JTAG TCLKR input]——–
There is no hardware for measuring the JTAG TCLK frequency.
—–[Perform the standard path-length test on the JTAG IR and DR]———–
This path-length test uses blocks of 64 32-bit words.
The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 6 bits.
The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.
—–[Perform the Integrity scan-test on the JTAG IR]————————
This test will use blocks of 64 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG IR Integrity scan-test has succeeded.
—–[Perform the Integrity scan-test on the JTAG DR]————————
This test will use blocks of 64 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG DR Integrity scan-test has succeeded.
[End: Texas Instruments XDS100v2 USB Debug Probe_0]
但我按下debug燒入後卻一直重複出現以下兩個問題
C28xx_CPU1: Error connecting to the target: (Error -1135 @ 0x0) The debug probe reported an error. Confirm debug probe configuration and connections, reset the debug probe, and retry the operation. (Emulation package 7.0.48.0)
C28xx_CPU1: Error connecting to the target: (Error -1015 @ 0x0) Device is not responding to the request. Device may be locked, or the debug probe connection may be unreliable. Unlock the device if possible (e.g. use wait in reset mode, and power-cycle the board). If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 7.0.48.0)
期間我嘗試過以下的量測：
1. 查看晶片的所有VDDIO與GND是否有正確接上，量測結果都有。
2. 更換過另外兩塊相同電路去燒入也出現一樣的失敗。
3.查看nRXS pin也是都有出現250usec low / 27.5msec high的訊號。
4. 查看TMS、TDI、TDO、nReset與TCK pin都看到燒入的初期有訊號交握，且所有pin的訊號都沒有失真。
5. 嘗試將VREGENZ pin pull high，並在所有VDD pin上外加1.2V，結果還是無法燒入。
6. 確認72與84 pin都是pull high讓晶片work在Get Mode。
7. 嘗試更換新的晶片也出現一樣的失敗。
8. 將我的JTAG燒入器拿去燒入F28035程式至F28035晶片結果可以(這樣看來我燒入器應該是沒問題的)
9. 嘗試用Uniflash燒入也一樣沒用。
請問我還有什麼沒有注意到或什麼狀況會導致跟我一樣的問題的嗎???
謝謝您們的關注
Don-Liu
Susan Yang：
根据您的错误提示应该是被锁了
您可以看一下wiki链接
This error is caused by the inability of the debug probe to communicate with the device. This can be caused by a number of sources but the most common are:
The device is locked, which can be unlocked by trying one of the methods shown at this forum thread or using Uniflash.
There are hardware problems, which can have multiple root causes:
各位先進前輩大家好!
我有一個F28075晶片無法燒入程式的問題想要在這裡請教
首先我參照可以正常運作的F28035電路圖與F2837x controlCARD的設計圖去設計我的F28075電路，
在電路完成後我先嘗試
測試JTAG connection結果如下
[Start: Texas Instruments XDS100v2 USB Debug Probe_0]
Execute the command:
%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity
[Result]
—–[Print the board config pathname(s)]————————————
C:\Users\Don_Liu\AppData\Local\TEXASI~1\
CCS\ti\3\0\BrdDat\testBoard.dat
—–[Print the reset-command software log-file]—————————–
This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesusb.dll'.
The library build date was 'Jul 21 2017'.
The library build time was '19:36:41'.
The library package version is '7.0.48.0'.
The library component version is '35.35.0.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.
—–[Print the reset-command hardware log-file]—————————–
The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).
—–[The log-file for the JTAG TCLK output generated from the PLL]———-
There is no hardware for programming the JTAG TCLK frequency.
—–[Measure the source and frequency of the final JTAG TCLKR input]——–
There is no hardware for measuring the JTAG TCLK frequency.
—–[Perform the standard path-length test on the JTAG IR and DR]———–
This path-length test uses blocks of 64 32-bit words.
The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 6 bits.
The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.
—–[Perform the Integrity scan-test on the JTAG IR]————————
This test will use blocks of 64 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG IR Integrity scan-test has succeeded.
—–[Perform the Integrity scan-test on the JTAG DR]————————
This test will use blocks of 64 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG DR Integrity scan-test has succeeded.
[End: Texas Instruments XDS100v2 USB Debug Probe_0]
但我按下debug燒入後卻一直重複出現以下兩個問題
C28xx_CPU1: Error connecting to the target: (Error -1135 @ 0x0) The debug probe reported an error. Confirm debug probe configuration and connections, reset the debug probe, and retry the operation. (Emulation package 7.0.48.0)
C28xx_CPU1: Error connecting to the target: (Error -1015 @ 0x0) Device is not responding to the request. Device may be locked, or the debug probe connection may be unreliable. Unlock the device if possible (e.g. use wait in reset mode, and power-cycle the board). If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 7.0.48.0)
期間我嘗試過以下的量測：
1. 查看晶片的所有VDDIO與GND是否有正確接上，量測結果都有。
2. 更換過另外兩塊相同電路去燒入也出現一樣的失敗。
3.查看nRXS pin也是都有出現250usec low / 27.5msec high的訊號。
4. 查看TMS、TDI、TDO、nReset與TCK pin都看到燒入的初期有訊號交握，且所有pin的訊號都沒有失真。
5. 嘗試將VREGENZ pin pull high，並在所有VDD pin上外加1.2V，結果還是無法燒入。
6. 確認72與84 pin都是pull high讓晶片work在Get Mode。
7. 嘗試更換新的晶片也出現一樣的失敗。
8. 將我的JTAG燒入器拿去燒入F28035程式至F28035晶片結果可以(這樣看來我燒入器應該是沒問題的)
9. 嘗試用Uniflash燒入也一樣沒用。
請問我還有什麼沒有注意到或什麼狀況會導致跟我一樣的問題的嗎???
謝謝您們的關注
Don-Liu
Liu Don：
回复 mangui zhang:
Hi
請問clkout腳指的是JTAG的TCK腳嗎??
如果是的話，我量測是有訊號在動作的!!
謝謝您寶貴的建議
Don
各位先進前輩大家好!
我有一個F28075晶片無法燒入程式的問題想要在這裡請教
首先我參照可以正常運作的F28035電路圖與F2837x controlCARD的設計圖去設計我的F28075電路，
在電路完成後我先嘗試
測試JTAG connection結果如下
[Start: Texas Instruments XDS100v2 USB Debug Probe_0]
Execute the command:
%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity
[Result]
—–[Print the board config pathname(s)]————————————
C:\Users\Don_Liu\AppData\Local\TEXASI~1\
CCS\ti\3\0\BrdDat\testBoard.dat
—–[Print the reset-command software log-file]—————————–
This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesusb.dll'.
The library build date was 'Jul 21 2017'.
The library build time was '19:36:41'.
The library package version is '7.0.48.0'.
The library component version is '35.35.0.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.
—–[Print the reset-command hardware log-file]—————————–
The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).
—–[The log-file for the JTAG TCLK output generated from the PLL]———-
There is no hardware for programming the JTAG TCLK frequency.
—–[Measure the source and frequency of the final JTAG TCLKR input]——–
There is no hardware for measuring the JTAG TCLK frequency.
—–[Perform the standard path-length test on the JTAG IR and DR]———–
This path-length test uses blocks of 64 32-bit words.
The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 6 bits.
The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.
—–[Perform the Integrity scan-test on the JTAG IR]————————
This test will use blocks of 64 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG IR Integrity scan-test has succeeded.
—–[Perform the Integrity scan-test on the JTAG DR]————————
This test will use blocks of 64 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG DR Integrity scan-test has succeeded.
[End: Texas Instruments XDS100v2 USB Debug Probe_0]
但我按下debug燒入後卻一直重複出現以下兩個問題
C28xx_CPU1: Error connecting to the target: (Error -1135 @ 0x0) The debug probe reported an error. Confirm debug probe configuration and connections, reset the debug probe, and retry the operation. (Emulation package 7.0.48.0)
C28xx_CPU1: Error connecting to the target: (Error -1015 @ 0x0) Device is not responding to the request. Device may be locked, or the debug probe connection may be unreliable. Unlock the device if possible (e.g. use wait in reset mode, and power-cycle the board). If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 7.0.48.0)
期間我嘗試過以下的量測：
1. 查看晶片的所有VDDIO與GND是否有正確接上，量測結果都有。
2. 更換過另外兩塊相同電路去燒入也出現一樣的失敗。
3.查看nRXS pin也是都有出現250usec low / 27.5msec high的訊號。
4. 查看TMS、TDI、TDO、nReset與TCK pin都看到燒入的初期有訊號交握，且所有pin的訊號都沒有失真。
5. 嘗試將VREGENZ pin pull high，並在所有VDD pin上外加1.2V，結果還是無法燒入。
6. 確認72與84 pin都是pull high讓晶片work在Get Mode。
7. 嘗試更換新的晶片也出現一樣的失敗。
8. 將我的JTAG燒入器拿去燒入F28035程式至F28035晶片結果可以(這樣看來我燒入器應該是沒問題的)
9. 嘗試用Uniflash燒入也一樣沒用。
請問我還有什麼沒有注意到或什麼狀況會導致跟我一樣的問題的嗎???
謝謝您們的關注
Don-Liu
Liu Don：
回复 Susan Yang:
Hi Susan,
我參考您提供的連結內如作了以下的測試：
1. 換一條通訊線，結果還是沒有用，出現一樣的error，而這兩條通訊現在其他地方都可以正常使用的。
2. 將晶片的第84腳接地，使晶片操作在Wait Boot Mode，然後嘗試使用Uniflash去讀取flash的內容，結果失敗，完全無法讀取到Flash的內容，因此也查不到Flash的password的數值。
3. 控制器摸起來沒有很熱的跡象。
4. VDDIO電源量測沒有異常。
但我有發現一個問題是關於nXRS pin的問題，
我比對可以燒入的F28035晶片在燒入時，當nReset pin pull low之後，我的 nXRS pin會停止250usec low / 27.5msec high的動作，轉為always high, 但是我發現F28075晶片燒入時nReset pin pull low之後nXRS pin不會停止250usec low / 27.5msec high的動作，所以我懷疑是因為nXRS pin不斷Reset晶片導致我的程式燒不進去，請問有甚麼辦法可以停止nXRS pin的Reset的嗎??
感謝您的回覆
Don
各位先進前輩大家好!
我有一個F28075晶片無法燒入程式的問題想要在這裡請教
首先我參照可以正常運作的F28035電路圖與F2837x controlCARD的設計圖去設計我的F28075電路，
在電路完成後我先嘗試
測試JTAG connection結果如下
[Start: Texas Instruments XDS100v2 USB Debug Probe_0]
Execute the command:
%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity
[Result]
—–[Print the board config pathname(s)]————————————
C:\Users\Don_Liu\AppData\Local\TEXASI~1\
CCS\ti\3\0\BrdDat\testBoard.dat
—–[Print the reset-command software log-file]—————————–
This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesusb.dll'.
The library build date was 'Jul 21 2017'.
The library build time was '19:36:41'.
The library package version is '7.0.48.0'.
The library component version is '35.35.0.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.
—–[Print the reset-command hardware log-file]—————————–
The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).
—–[The log-file for the JTAG TCLK output generated from the PLL]———-
There is no hardware for programming the JTAG TCLK frequency.
—–[Measure the source and frequency of the final JTAG TCLKR input]——–
There is no hardware for measuring the JTAG TCLK frequency.
—–[Perform the standard path-length test on the JTAG IR and DR]———–
This path-length test uses blocks of 64 32-bit words.
The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 6 bits.
The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.
—–[Perform the Integrity scan-test on the JTAG IR]————————
This test will use blocks of 64 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG IR Integrity scan-test has succeeded.
—–[Perform the Integrity scan-test on the JTAG DR]————————
This test will use blocks of 64 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG DR Integrity scan-test has succeeded.
[End: Texas Instruments XDS100v2 USB Debug Probe_0]
但我按下debug燒入後卻一直重複出現以下兩個問題
C28xx_CPU1: Error connecting to the target: (Error -1135 @ 0x0) The debug probe reported an error. Confirm debug probe configuration and connections, reset the debug probe, and retry the operation. (Emulation package 7.0.48.0)
C28xx_CPU1: Error connecting to the target: (Error -1015 @ 0x0) Device is not responding to the request. Device may be locked, or the debug probe connection may be unreliable. Unlock the device if possible (e.g. use wait in reset mode, and power-cycle the board). If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 7.0.48.0)
期間我嘗試過以下的量測：
1. 查看晶片的所有VDDIO與GND是否有正確接上，量測結果都有。
2. 更換過另外兩塊相同電路去燒入也出現一樣的失敗。
3.查看nRXS pin也是都有出現250usec low / 27.5msec high的訊號。
4. 查看TMS、TDI、TDO、nReset與TCK pin都看到燒入的初期有訊號交握，且所有pin的訊號都沒有失真。
5. 嘗試將VREGENZ pin pull high，並在所有VDD pin上外加1.2V，結果還是無法燒入。
6. 確認72與84 pin都是pull high讓晶片work在Get Mode。
7. 嘗試更換新的晶片也出現一樣的失敗。
8. 將我的JTAG燒入器拿去燒入F28035程式至F28035晶片結果可以(這樣看來我燒入器應該是沒問題的)
9. 嘗試用Uniflash燒入也一樣沒用。
請問我還有什麼沒有注意到或什麼狀況會導致跟我一樣的問題的嗎???
謝謝您們的關注
Don-Liu
Susan Yang：
回复 Liu Don:
很高兴您能解决问题并分享答案
