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TMS320F28377多个epwm模块无法同步

使用器件:TMS320F28377S,封装为100pin

目的:使EPWM7与EPWM10载波移相180度

操作方法:根据数据手册EPWM7与EPWM10不属于同一个同步链,因此在EPWM7过零的时候产生同步信号,同时选择EMPW10的同步输入源为EPWM7,具体代码如下,结果显示EPWM7和EPWM10移相180度,怀疑EPWM7的同步触发信号未送到EPWM10,是否100pin引脚的不能这样操作?

    EALLOW;
    EPwm7Regs.TBPRD = TPRD_CLLC_Init;                          // Set timer period   增减计数:200=200MHz/(500kHz*2)
    EPwm7Regs.TBPHS.bit.TBPHS = 0x0000;                   // Phase is 0
    EPwm7Regs.TBCTR = 0x0000;                              // Clear counter
    // Setup TBCLK
    // TBCLK=SYSCLKOUT/(HSPCLKDIV×CLKDIV)
    EPwm7Regs.TBCTL.bit.CTRMODE   = TB_COUNT_UPDOWN;           // Count up_down
    EPwm7Regs.TBCTL.bit.PRDLD     = TB_SHADOW;
    EPwm7Regs.TBCTL.bit.PHSEN     = TB_DISABLE;             // 01表示Enable phase loading
    EPwm7Regs.TBCTL.bit.SYNCOSEL  = TB_CTR_ZERO;            // 01表示同步由EPWM7产生
    EPwm7Regs.TBCTL.bit.HSPCLKDIV = __HSPCLKDIV;               // Clock ratio to SYSCLKOUT
    EPwm7Regs.TBCTL.bit.CLKDIV    = __CLKDIV;               // 例程的TBCLK=200MHz/(1*1)=2000MHz
   EPwm10Regs.TBPRD = TPRD_CLLC_Init;                          // Set timer period   增减计数:200=200MHz/(500kHz*2)
    EPwm10Regs.TBPHS.bit.TBPHS = 0;                       // Phase is 1800,为满足Q8与Q5同步
    EPwm10Regs.TBCTR = 0x0000;                              // Clear counter
    SyncSocRegs.SYNCSELECT.bit.EPWM10SYNCIN  = 0x10;        //同步源选择Epwm7
    EPwm10Regs.TBCTL.bit.CTRMODE   = TB_COUNT_UPDOWN;           // Count up down
    EPwm10Regs.TBCTL.bit.PRDLD     = TB_SHADOW;
    EPwm10Regs.TBCTL.bit.PHSEN     = TB_ENABLE;             // 01表示Enable phase loading
    EPwm10Regs.TBCTL.bit.SYNCOSEL  = TB_SYNC_DISABLE;            // 03表示同步由EPWM7产生,传到此,不再向下传递
    EPwm10Regs.TBCTL.bit.HSPCLKDIV = __HSPCLKDIV;               // Clock ratio to SYSCLKOUT
    EPwm10Regs.TBCTL.bit.CLKDIV    = __CLKDIV;               // 例程的TBCLK=200MHz/(1*1)=200MHz

Susan Yang:

您是否有设置下面的

使用器件:TMS320F28377S,封装为100pin

目的:使EPWM7与EPWM10载波移相180度

操作方法:根据数据手册EPWM7与EPWM10不属于同一个同步链,因此在EPWM7过零的时候产生同步信号,同时选择EMPW10的同步输入源为EPWM7,具体代码如下,结果显示EPWM7和EPWM10移相180度,怀疑EPWM7的同步触发信号未送到EPWM10,是否100pin引脚的不能这样操作?

    EALLOW;
    EPwm7Regs.TBPRD = TPRD_CLLC_Init;                          // Set timer period   增减计数:200=200MHz/(500kHz*2)
    EPwm7Regs.TBPHS.bit.TBPHS = 0x0000;                   // Phase is 0
    EPwm7Regs.TBCTR = 0x0000;                              // Clear counter
    // Setup TBCLK
    // TBCLK=SYSCLKOUT/(HSPCLKDIV×CLKDIV)
    EPwm7Regs.TBCTL.bit.CTRMODE   = TB_COUNT_UPDOWN;           // Count up_down
    EPwm7Regs.TBCTL.bit.PRDLD     = TB_SHADOW;
    EPwm7Regs.TBCTL.bit.PHSEN     = TB_DISABLE;             // 01表示Enable phase loading
    EPwm7Regs.TBCTL.bit.SYNCOSEL  = TB_CTR_ZERO;            // 01表示同步由EPWM7产生
    EPwm7Regs.TBCTL.bit.HSPCLKDIV = __HSPCLKDIV;               // Clock ratio to SYSCLKOUT
    EPwm7Regs.TBCTL.bit.CLKDIV    = __CLKDIV;               // 例程的TBCLK=200MHz/(1*1)=2000MHz
   EPwm10Regs.TBPRD = TPRD_CLLC_Init;                          // Set timer period   增减计数:200=200MHz/(500kHz*2)
    EPwm10Regs.TBPHS.bit.TBPHS = 0;                       // Phase is 1800,为满足Q8与Q5同步
    EPwm10Regs.TBCTR = 0x0000;                              // Clear counter
    SyncSocRegs.SYNCSELECT.bit.EPWM10SYNCIN  = 0x10;        //同步源选择Epwm7
    EPwm10Regs.TBCTL.bit.CTRMODE   = TB_COUNT_UPDOWN;           // Count up down
    EPwm10Regs.TBCTL.bit.PRDLD     = TB_SHADOW;
    EPwm10Regs.TBCTL.bit.PHSEN     = TB_ENABLE;             // 01表示Enable phase loading
    EPwm10Regs.TBCTL.bit.SYNCOSEL  = TB_SYNC_DISABLE;            // 03表示同步由EPWM7产生,传到此,不再向下传递
    EPwm10Regs.TBCTL.bit.HSPCLKDIV = __HSPCLKDIV;               // Clock ratio to SYSCLKOUT
    EPwm10Regs.TBCTL.bit.CLKDIV    = __CLKDIV;               // 例程的TBCLK=200MHz/(1*1)=200MHz

Susan Yang:而且同步信号每次在模块间传输会有2个SYSCLK的delay,不是完全准确的同步的,所以同步链路越长,delay就会累积越多。

使用器件:TMS320F28377S,封装为100pin

目的:使EPWM7与EPWM10载波移相180度

操作方法:根据数据手册EPWM7与EPWM10不属于同一个同步链,因此在EPWM7过零的时候产生同步信号,同时选择EMPW10的同步输入源为EPWM7,具体代码如下,结果显示EPWM7和EPWM10移相180度,怀疑EPWM7的同步触发信号未送到EPWM10,是否100pin引脚的不能这样操作?

    EALLOW;
    EPwm7Regs.TBPRD = TPRD_CLLC_Init;                          // Set timer period   增减计数:200=200MHz/(500kHz*2)
    EPwm7Regs.TBPHS.bit.TBPHS = 0x0000;                   // Phase is 0
    EPwm7Regs.TBCTR = 0x0000;                              // Clear counter
    // Setup TBCLK
    // TBCLK=SYSCLKOUT/(HSPCLKDIV×CLKDIV)
    EPwm7Regs.TBCTL.bit.CTRMODE   = TB_COUNT_UPDOWN;           // Count up_down
    EPwm7Regs.TBCTL.bit.PRDLD     = TB_SHADOW;
    EPwm7Regs.TBCTL.bit.PHSEN     = TB_DISABLE;             // 01表示Enable phase loading
    EPwm7Regs.TBCTL.bit.SYNCOSEL  = TB_CTR_ZERO;            // 01表示同步由EPWM7产生
    EPwm7Regs.TBCTL.bit.HSPCLKDIV = __HSPCLKDIV;               // Clock ratio to SYSCLKOUT
    EPwm7Regs.TBCTL.bit.CLKDIV    = __CLKDIV;               // 例程的TBCLK=200MHz/(1*1)=2000MHz
   EPwm10Regs.TBPRD = TPRD_CLLC_Init;                          // Set timer period   增减计数:200=200MHz/(500kHz*2)
    EPwm10Regs.TBPHS.bit.TBPHS = 0;                       // Phase is 1800,为满足Q8与Q5同步
    EPwm10Regs.TBCTR = 0x0000;                              // Clear counter
    SyncSocRegs.SYNCSELECT.bit.EPWM10SYNCIN  = 0x10;        //同步源选择Epwm7
    EPwm10Regs.TBCTL.bit.CTRMODE   = TB_COUNT_UPDOWN;           // Count up down
    EPwm10Regs.TBCTL.bit.PRDLD     = TB_SHADOW;
    EPwm10Regs.TBCTL.bit.PHSEN     = TB_ENABLE;             // 01表示Enable phase loading
    EPwm10Regs.TBCTL.bit.SYNCOSEL  = TB_SYNC_DISABLE;            // 03表示同步由EPWM7产生,传到此,不再向下传递
    EPwm10Regs.TBCTL.bit.HSPCLKDIV = __HSPCLKDIV;               // Clock ratio to SYSCLKOUT
    EPwm10Regs.TBCTL.bit.CLKDIV    = __CLKDIV;               // 例程的TBCLK=200MHz/(1*1)=200MHz

user4104929:

回复 Susan Yang:

有的,在配置EPWM模块前先使能了模块时钟,然后关掉同步,待配置好后再打开同步,但是现在的结果显示EPWM7和EPWM10是完全同步的,按我的配置应该是移相180度的,感觉像是7的同步信号未传输到10

使用器件:TMS320F28377S,封装为100pin

目的:使EPWM7与EPWM10载波移相180度

操作方法:根据数据手册EPWM7与EPWM10不属于同一个同步链,因此在EPWM7过零的时候产生同步信号,同时选择EMPW10的同步输入源为EPWM7,具体代码如下,结果显示EPWM7和EPWM10移相180度,怀疑EPWM7的同步触发信号未送到EPWM10,是否100pin引脚的不能这样操作?

    EALLOW;
    EPwm7Regs.TBPRD = TPRD_CLLC_Init;                          // Set timer period   增减计数:200=200MHz/(500kHz*2)
    EPwm7Regs.TBPHS.bit.TBPHS = 0x0000;                   // Phase is 0
    EPwm7Regs.TBCTR = 0x0000;                              // Clear counter
    // Setup TBCLK
    // TBCLK=SYSCLKOUT/(HSPCLKDIV×CLKDIV)
    EPwm7Regs.TBCTL.bit.CTRMODE   = TB_COUNT_UPDOWN;           // Count up_down
    EPwm7Regs.TBCTL.bit.PRDLD     = TB_SHADOW;
    EPwm7Regs.TBCTL.bit.PHSEN     = TB_DISABLE;             // 01表示Enable phase loading
    EPwm7Regs.TBCTL.bit.SYNCOSEL  = TB_CTR_ZERO;            // 01表示同步由EPWM7产生
    EPwm7Regs.TBCTL.bit.HSPCLKDIV = __HSPCLKDIV;               // Clock ratio to SYSCLKOUT
    EPwm7Regs.TBCTL.bit.CLKDIV    = __CLKDIV;               // 例程的TBCLK=200MHz/(1*1)=2000MHz
   EPwm10Regs.TBPRD = TPRD_CLLC_Init;                          // Set timer period   增减计数:200=200MHz/(500kHz*2)
    EPwm10Regs.TBPHS.bit.TBPHS = 0;                       // Phase is 1800,为满足Q8与Q5同步
    EPwm10Regs.TBCTR = 0x0000;                              // Clear counter
    SyncSocRegs.SYNCSELECT.bit.EPWM10SYNCIN  = 0x10;        //同步源选择Epwm7
    EPwm10Regs.TBCTL.bit.CTRMODE   = TB_COUNT_UPDOWN;           // Count up down
    EPwm10Regs.TBCTL.bit.PRDLD     = TB_SHADOW;
    EPwm10Regs.TBCTL.bit.PHSEN     = TB_ENABLE;             // 01表示Enable phase loading
    EPwm10Regs.TBCTL.bit.SYNCOSEL  = TB_SYNC_DISABLE;            // 03表示同步由EPWM7产生,传到此,不再向下传递
    EPwm10Regs.TBCTL.bit.HSPCLKDIV = __HSPCLKDIV;               // Clock ratio to SYSCLKOUT
    EPwm10Regs.TBCTL.bit.CLKDIV    = __CLKDIV;               // 例程的TBCLK=200MHz/(1*1)=200MHz

user4104929:

回复 Susan Yang:

可能表述不太清楚,我是想要EPWM7和EPWM10移相180度,所以使能了移相寄存器,但是目前结果来看并没有移相,似乎是EPWM7的同步信号并没有被EPWM10接收

使用器件:TMS320F28377S,封装为100pin

目的:使EPWM7与EPWM10载波移相180度

操作方法:根据数据手册EPWM7与EPWM10不属于同一个同步链,因此在EPWM7过零的时候产生同步信号,同时选择EMPW10的同步输入源为EPWM7,具体代码如下,结果显示EPWM7和EPWM10移相180度,怀疑EPWM7的同步触发信号未送到EPWM10,是否100pin引脚的不能这样操作?

    EALLOW;
    EPwm7Regs.TBPRD = TPRD_CLLC_Init;                          // Set timer period   增减计数:200=200MHz/(500kHz*2)
    EPwm7Regs.TBPHS.bit.TBPHS = 0x0000;                   // Phase is 0
    EPwm7Regs.TBCTR = 0x0000;                              // Clear counter
    // Setup TBCLK
    // TBCLK=SYSCLKOUT/(HSPCLKDIV×CLKDIV)
    EPwm7Regs.TBCTL.bit.CTRMODE   = TB_COUNT_UPDOWN;           // Count up_down
    EPwm7Regs.TBCTL.bit.PRDLD     = TB_SHADOW;
    EPwm7Regs.TBCTL.bit.PHSEN     = TB_DISABLE;             // 01表示Enable phase loading
    EPwm7Regs.TBCTL.bit.SYNCOSEL  = TB_CTR_ZERO;            // 01表示同步由EPWM7产生
    EPwm7Regs.TBCTL.bit.HSPCLKDIV = __HSPCLKDIV;               // Clock ratio to SYSCLKOUT
    EPwm7Regs.TBCTL.bit.CLKDIV    = __CLKDIV;               // 例程的TBCLK=200MHz/(1*1)=2000MHz
   EPwm10Regs.TBPRD = TPRD_CLLC_Init;                          // Set timer period   增减计数:200=200MHz/(500kHz*2)
    EPwm10Regs.TBPHS.bit.TBPHS = 0;                       // Phase is 1800,为满足Q8与Q5同步
    EPwm10Regs.TBCTR = 0x0000;                              // Clear counter
    SyncSocRegs.SYNCSELECT.bit.EPWM10SYNCIN  = 0x10;        //同步源选择Epwm7
    EPwm10Regs.TBCTL.bit.CTRMODE   = TB_COUNT_UPDOWN;           // Count up down
    EPwm10Regs.TBCTL.bit.PRDLD     = TB_SHADOW;
    EPwm10Regs.TBCTL.bit.PHSEN     = TB_ENABLE;             // 01表示Enable phase loading
    EPwm10Regs.TBCTL.bit.SYNCOSEL  = TB_SYNC_DISABLE;            // 03表示同步由EPWM7产生,传到此,不再向下传递
    EPwm10Regs.TBCTL.bit.HSPCLKDIV = __HSPCLKDIV;               // Clock ratio to SYSCLKOUT
    EPwm10Regs.TBCTL.bit.CLKDIV    = __CLKDIV;               // 例程的TBCLK=200MHz/(1*1)=200MHz

Susan Yang:

回复 user4104929:

是不是高亮部分的设置问题?

使用器件:TMS320F28377S,封装为100pin

目的:使EPWM7与EPWM10载波移相180度

操作方法:根据数据手册EPWM7与EPWM10不属于同一个同步链,因此在EPWM7过零的时候产生同步信号,同时选择EMPW10的同步输入源为EPWM7,具体代码如下,结果显示EPWM7和EPWM10移相180度,怀疑EPWM7的同步触发信号未送到EPWM10,是否100pin引脚的不能这样操作?

    EALLOW;
    EPwm7Regs.TBPRD = TPRD_CLLC_Init;                          // Set timer period   增减计数:200=200MHz/(500kHz*2)
    EPwm7Regs.TBPHS.bit.TBPHS = 0x0000;                   // Phase is 0
    EPwm7Regs.TBCTR = 0x0000;                              // Clear counter
    // Setup TBCLK
    // TBCLK=SYSCLKOUT/(HSPCLKDIV×CLKDIV)
    EPwm7Regs.TBCTL.bit.CTRMODE   = TB_COUNT_UPDOWN;           // Count up_down
    EPwm7Regs.TBCTL.bit.PRDLD     = TB_SHADOW;
    EPwm7Regs.TBCTL.bit.PHSEN     = TB_DISABLE;             // 01表示Enable phase loading
    EPwm7Regs.TBCTL.bit.SYNCOSEL  = TB_CTR_ZERO;            // 01表示同步由EPWM7产生
    EPwm7Regs.TBCTL.bit.HSPCLKDIV = __HSPCLKDIV;               // Clock ratio to SYSCLKOUT
    EPwm7Regs.TBCTL.bit.CLKDIV    = __CLKDIV;               // 例程的TBCLK=200MHz/(1*1)=2000MHz
   EPwm10Regs.TBPRD = TPRD_CLLC_Init;                          // Set timer period   增减计数:200=200MHz/(500kHz*2)
    EPwm10Regs.TBPHS.bit.TBPHS = 0;                       // Phase is 1800,为满足Q8与Q5同步
    EPwm10Regs.TBCTR = 0x0000;                              // Clear counter
    SyncSocRegs.SYNCSELECT.bit.EPWM10SYNCIN  = 0x10;        //同步源选择Epwm7
    EPwm10Regs.TBCTL.bit.CTRMODE   = TB_COUNT_UPDOWN;           // Count up down
    EPwm10Regs.TBCTL.bit.PRDLD     = TB_SHADOW;
    EPwm10Regs.TBCTL.bit.PHSEN     = TB_ENABLE;             // 01表示Enable phase loading
    EPwm10Regs.TBCTL.bit.SYNCOSEL  = TB_SYNC_DISABLE;            // 03表示同步由EPWM7产生,传到此,不再向下传递
    EPwm10Regs.TBCTL.bit.HSPCLKDIV = __HSPCLKDIV;               // Clock ratio to SYSCLKOUT
    EPwm10Regs.TBCTL.bit.CLKDIV    = __CLKDIV;               // 例程的TBCLK=200MHz/(1*1)=200MHz

user4104929:

回复 Susan Yang:

似乎不是,我在贴出来的代码里已经将移相使能,在移相寄存器中无论写入值是多少,EPWM7和EPWM10都没有产生移相。

使用器件:TMS320F28377S,封装为100pin

目的:使EPWM7与EPWM10载波移相180度

操作方法:根据数据手册EPWM7与EPWM10不属于同一个同步链,因此在EPWM7过零的时候产生同步信号,同时选择EMPW10的同步输入源为EPWM7,具体代码如下,结果显示EPWM7和EPWM10移相180度,怀疑EPWM7的同步触发信号未送到EPWM10,是否100pin引脚的不能这样操作?

    EALLOW;
    EPwm7Regs.TBPRD = TPRD_CLLC_Init;                          // Set timer period   增减计数:200=200MHz/(500kHz*2)
    EPwm7Regs.TBPHS.bit.TBPHS = 0x0000;                   // Phase is 0
    EPwm7Regs.TBCTR = 0x0000;                              // Clear counter
    // Setup TBCLK
    // TBCLK=SYSCLKOUT/(HSPCLKDIV×CLKDIV)
    EPwm7Regs.TBCTL.bit.CTRMODE   = TB_COUNT_UPDOWN;           // Count up_down
    EPwm7Regs.TBCTL.bit.PRDLD     = TB_SHADOW;
    EPwm7Regs.TBCTL.bit.PHSEN     = TB_DISABLE;             // 01表示Enable phase loading
    EPwm7Regs.TBCTL.bit.SYNCOSEL  = TB_CTR_ZERO;            // 01表示同步由EPWM7产生
    EPwm7Regs.TBCTL.bit.HSPCLKDIV = __HSPCLKDIV;               // Clock ratio to SYSCLKOUT
    EPwm7Regs.TBCTL.bit.CLKDIV    = __CLKDIV;               // 例程的TBCLK=200MHz/(1*1)=2000MHz
   EPwm10Regs.TBPRD = TPRD_CLLC_Init;                          // Set timer period   增减计数:200=200MHz/(500kHz*2)
    EPwm10Regs.TBPHS.bit.TBPHS = 0;                       // Phase is 1800,为满足Q8与Q5同步
    EPwm10Regs.TBCTR = 0x0000;                              // Clear counter
    SyncSocRegs.SYNCSELECT.bit.EPWM10SYNCIN  = 0x10;        //同步源选择Epwm7
    EPwm10Regs.TBCTL.bit.CTRMODE   = TB_COUNT_UPDOWN;           // Count up down
    EPwm10Regs.TBCTL.bit.PRDLD     = TB_SHADOW;
    EPwm10Regs.TBCTL.bit.PHSEN     = TB_ENABLE;             // 01表示Enable phase loading
    EPwm10Regs.TBCTL.bit.SYNCOSEL  = TB_SYNC_DISABLE;            // 03表示同步由EPWM7产生,传到此,不再向下传递
    EPwm10Regs.TBCTL.bit.HSPCLKDIV = __HSPCLKDIV;               // Clock ratio to SYSCLKOUT
    EPwm10Regs.TBCTL.bit.CLKDIV    = __CLKDIV;               // 例程的TBCLK=200MHz/(1*1)=200MHz

Susan Yang:

回复 user4104929:

您可以看一下  

14.13.7 Practical Applications Using Phase Control Between PWM Modules

Here, TBPRD = 600 for both master and slave. For the slave, TBPHS = 200 (that is, 200/600 X 360° = 120°).

按照给出的说明

TBPHS/TBPRD X 360° = 180°

您可以试一下

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