TI中文支持网我打算在c5515中实现一个简易的MP3，预想是先将MP3转换为PCM格式，然后在aic3204中播放，可不知该怎么配置。
void aic3204_init_mono(void)
{
SYS_EXBUSSEL = 0x6100; // Enable I2C bus
USBSTK5515_I2C_init( ); // Initialize I2C
/* Configure AIC3204 */
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 1, 0x01 ); // Reset codec
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 1, 0x08 ); // Disable crude AVDD generation from DVDD
AIC3204_rset( 2, 0x01 ); // Enable Analog Blocks, use LDO power
AIC3204_rset( 10, 0x00 ); //#Set the input common mode to 0.9V
AIC3204_rset( 61, 0x00 ); //#Set ADC PTM_R4
AIC3204_rset( 71, 0x00 ); //#Set MicPGA startup delay to 3.1ms
AIC3204_rset( 123, 0x01 ); //#Set the REF charging time to 40ms
/* PLL and Clocks config and Power Up */
AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 27, 0x4d ); // BCLK and WCLK is set as o/p to AIC3204(Master) interface DSP
AIC3204_rset( 28, 0x02 ); //#Data offset value ( ajout de 1 BCLK's)
AIC3204_rset( 29, 0x08 ); //# Audio interface set
AIC3204_rset( 61, 0x01 ); //ADC Signal Processing Block Control Register
AIC3204_rset( 60, 0x8 ); //DAC Signal Processing Block Control Register
AIC3204_rset( 4, 3 ); // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
AIC3204_rset( 6, 8 ); // PLL setting: J=8
AIC3204_rset( 7, 0x07 ); // PLL setting: HI_BYTE(D=1680)
AIC3204_rset( 8, 0x80 ); // PLL setting: LO_BYTE(D=1680)
AIC3204_rset( 30, 0xc0 ); // For 32 bit clocks per frame in Master mode ONLY
// BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
AIC3204_rset( 5, 0x91 ); // PLL setting: Power up PLL, P=1 and R=1
AIC3204_rset( 13, 03 ); // Hi_Byte(DOSR) for DOSR = 768 decimal or 0x0300 DAC oversamppling
AIC3204_rset( 14, 0x00 ); // Lo_Byte(DOSR) for DOSR = 768 decimal or 0x0300
AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 decimal or 0x80 for decimation filters 1 to 6
AIC3204_rset( 11, 0x88 ); // Power up NDAC and set NDAC value to 2
AIC3204_rset( 12, 0x82 ); // Power up MDAC and set MDAC value to 8
AIC3204_rset( 18, 0x88 ); // Power up NADC and set NADC value to 8
AIC3204_rset( 19, 0x8c ); // Power up MADC and set MADC value to 12
AIC3204_rset( 81, 0x00 ); // Power down Left and Right ADC
AIC3204_rset( 63, 0x14 ); // Power down left,right data paths and set channel
AIC3204_rset( 61, 2 ); // PRB_R2
// set biquad A to low pass fc = 3628
AIC3204_rset( 0, 8 ); // Select page 8
AIC3204_rset( 36, 0x6A ); // Left N0 H
AIC3204_rset( 37, 0xC3 ); // Left N0 M
AIC3204_rset( 38, 0x6F ); // Left N0 L
AIC3204_rset( 40, 0x35 ); // Left N1 H
AIC3204_rset( 41, 0x61 ); // Left N1 M
AIC3204_rset( 42, 0xB7 ); // Left N1 L
AIC3204_rset( 44, 0x00 ); // Left N2 H
AIC3204_rset( 45, 0x00 ); // Left N2 M
AIC3204_rset( 46, 0x00 ); // Left N2 L
AIC3204_rset( 48, 0xD5 ); // Left D1 H
AIC3204_rset( 49, 0x3C ); // Left D1 M
AIC3204_rset( 50, 0x91 ); // Left D1 L
AIC3204_rset( 52, 0x00 ); // Left D2 H
AIC3204_rset( 53, 0x00 ); // Left D2 M
AIC3204_rset( 54, 0x00 ); // Left D2 L
AIC3204_rset( 0, 9 ); // Select page 9
AIC3204_rset( 44, 0x6F ); // Right N0 H
AIC3204_rset( 45, 0x96 ); // Right N0 M
AIC3204_rset( 46, 0x52 ); // Right N0 L
AIC3204_rset( 48, 0x37 ); // Right N1 H
AIC3204_rset( 49, 0xCB ); // Right N1 M
AIC3204_rset( 50, 0x29 ); // Right N1 L
AIC3204_rset( 52, 0x00 ); // Right N2 H
AIC3204_rset( 53, 0x00 ); // Right N2 M
AIC3204_rset( 54, 0x00 ); // Right N2 L
AIC3204_rset( 56, 0xD0 ); // Right D1 H
AIC3204_rset( 57, 0x69 ); // Right D1 M
AIC3204_rset( 58, 0xAD ); // Right D1 L
AIC3204_rset( 60, 0x00 ); // Right D2 H
AIC3204_rset( 61, 0x00 ); // Right D2 M
AIC3204_rset( 62, 0x00 ); // Right D2 L
/* DAC ROUTING and Power Up */
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 9, 0x30 ); //# OUTPUT DRIVER POWER CONTROL hp->ON lineout->OFF mixer->OFF
AIC3204_rset( 10, 0x03 ); //#COMMON MODE CONTROL REGISTER Output of HP is powered by LDOIN
AIC3204_rset( 11, 0x10 ); //Over Current detection is enabled for HPL & HPR
AIC3204_rset( 12, 0x08 ); //# Left DAC (+) -> HPL
AIC3204_rset( 13, 0x00 ); //# Left DAC (-) -> HPR
AIC3204_rset( 14, 0x00 ); //# LOL is not routed
AIC3204_rset( 15, 0x00 ); //# LOR is not routed
AIC3204_rset( 16, 0x3c ); // HPL Driver gain setting register Unmute HPL , 0dB gain
AIC3204_rset( 17, 0x3c ); // volume de sortie headphone 0x00 -> 0dB 0x3A -> -6dB 0x1d -> +29dB
AIC3204_rset( 18, 0x40 ); //# LOL driver gain settings register
AIC3204_rset( 19, 0x40 ); //# LOL & LOR MUTED
AIC3204_rset( 20, 0x25 ); //#HEADPHONE DRIVER STARTUP Headphone amps power up slowly in 5.0 time constants / Headphone amps power up time is determined with 6K resistance
AIC3204_rset( 22, 0x00 ); //# IN1L to HPL volume control bypass 0dB
AIC3204_rset( 23, 0x00 ); //# IN1L to HPL volume control bypass 0dB
AIC3204_rset( 24, 0x00 ); //# MIXERAMP Left volume control
AIC3204_rset( 25, 0x00 );
AIC3204_rset( 51, 0x50 ); //# setting du micbias micbias = Vcc
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 64, 0x00 ); //#DAC L UNMUTED, R&L independant DAC R MUTED (mode differentiel)
//# 0x00 -> 0dB 0xFF -> -0.5dB 0x81 -> -63dB
AIC3204_rset( 65, 0x00 ); //# Left DAC channel digital volume control register
AIC3204_rset( 66, 0x00 ); //# Right DAC Channel Digital Volume Control Register
AIC3204_rset( 63, 0x90 ); //#DAC L switched ON, R OFF, soft-stepping enabled
/* ADC ROUTING and Power Up */
AIC3204_rset( 0, 1 ); // Select page 1
AIC3204_rset( 52, 0x30 ); //# IN2L -> Left MICPGA + 40K resistance
AIC3204_rset( 54, 0x30 ); //# IN2R -> Left MICPGA – 40K resistance
AIC3204_rset( 55, 0x00 ); //# Right MICPGA positive terminal input routing
AIC3204_rset( 57, 0x00 ); //# Right MICPGA negative terminal input routing
AIC3204_rset( 58, 0xbb ); //#Floating Input Configuration register
AIC3204_rset( 59, 0 ); // MIC_PGA_L unmute
AIC3204_rset( 60, 0 ); // MIC_PGA_R unmute
AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 81, 0x80 ); //#ADC right OFF & left ON
AIC3204_rset( 82, 0x08 ); //#ADC left UNMUTED right MUTED
AIC3204_rset( 83, 0x67 ); //#ADC left & right channel volume control
AIC3204_rset( 84, 0x67 ); //#ADC volume 20dB — 0x28 -12dB — 0x67
AIC3204_rset( 85, 0x81 ); //#ADC phase adjust register
AIC3204_rset( 0, 0 );
USBSTK5515_wait( 200 ); // Wait
// I2S settings
I2S0_SRGR = 0x0;
I2S0_CR = 0x8010;
I2S0_ICMR = 0x2b;
}
/* ———————————————————————— *
* *
* AIC3204 Tone *
* Output a 1 kHz tone through the HEADPHONE jack *
* *
* ———————————————————————— */
Int16 aic3204_tone_headphone(Int16* sinetable )
{
aic3204_init_mono();
Int16 i, sample;
/* Play Tone */
for ( i = 0 ; i < 50000; i++ )
{
while((XmitR & I2S0_IR) == 0); // Wait for transmit interrupt to be pending
//sample = sinetable[i];
sample = ((sinetable[i] &0xff) << 8) | ((sinetable[i] &0xff00) >> 8);
I2S0_W0_MSW_W = sample ; // 16 bit left channel transmit audio data
I2S0_W1_MSW_W = sample; // 16 bit right channel transmit audio data
}
/* Disble I2S */
I2S0_CR = 0x00;
return 0;
}
这是我的配置代码和调用代码，其中sinetable数组中储存了从pcm文件中读取的数据，希望给予帮助，谢谢
user151383853：
没有看到在调试中遇到了什么问题呢?
