TI中文支持网I2C初始化
void I2CA_Init(void)
{
// Initialize I2C
I2caRegs.I2CSAR = 0x0020; // Slave address – EEPROM control code
I2caRegs.I2CPSC.all = 7; // Prescaler – need 7-12 Mhz on module clk
I2caRegs.I2CCLKL = 10; // NOTE: must be non zero
I2caRegs.I2CCLKH = 5; // NOTE: must be non zero
I2caRegs.I2CIER.all =0x00; //0x24; // Enable SCD & ARDY interrupts
I2caRegs.I2CMDR.all = 0x0020; // Take I2C out of reset
// Stop I2C when suspended
I2caRegs.I2CFFTX.all = 0x00;//0x6000; // Enable FIFO mode and TXFIFO
I2caRegs.I2CFFRX.all = 0x00;//0x2040; // Enable RXFIFO, clear RXFFINT,
return;
}
I2C写函数
void I2CA_SendData(struct I2CMSG *msg,Uint16 addr,Uint16 type,Uint16 data)
{
Uint16 i;
while(I2caRegs.I2CMDR.bit.STP ==1);
I2caRegs.I2CSAR = addr; //Set slave address
while(I2caRegs.I2CSTR.bit.BB == 1);
I2caRegs.I2CCNT = 3; //Set count to 5 characters plus 2 address bytes
I2caRegs.I2CDXR = type; //Send eeprom high address
// I2caRegs.I2CMDR.bit.TRX = 1; //Set to Transmit mode
// I2caRegs.I2CMDR.bit.MST = 1; //Set to Master mode
// I2caRegs.I2CMDR.bit.FREE = 1; //Run in FREE mode
// I2caRegs.I2CMDR.bit.STP = 1; //Stop when internal counter becomes 0
// I2caRegs.I2CMDR.bit.STT = 1; //Send the start bit, transmission will follow
// while(I2caRegs.I2CSTR.bit.XRDY == 0){}; //Do nothing till data is shifted out
// I2caRegs.I2CDXR = type; //Send eeprom low address
I2caRegs.I2CMDR.all = 0x6E20;
for(i = 0; i < 2; i++){
while(I2caRegs.I2CSTR.bit.XRDY == 0){}; //Do nothing till data is shifted out
// while(I2caRegs.I2CFFTX.bit.TXFFST == 16);
I2caRegs.I2CDXR = data>>((1-i)*8); //Send out the message
}
}
在for(;;)
{
LoopCount++;
if (LoopCount >4000)
{
LoopCount =0;
I2CA_SendData()
}
具体为这样操作的，但是写一段时间会停在while(I2caRegs.I2CSTR.bit.XRDY == 0){};此处，求大牛帮忙看一下
}
B Z：
跪求TI大牛帮忙看下
user151383853：
回复 B Z:
XRDY:
Transmit-data-ready interrupt flag bit. When not in FIFO mode, XRDY indicates that the data transmit register (I2CDXR) is ready to accept new data because the previous data has been copied from I2CDXR to the transmit shift register (I2CXSR). The CPU can poll XRDY or use the XRDY interrupt request (see Section 14.3.1). When in FIFO mode, use TXFFINT instead.
0 I2CDXR not ready. XRDY is cleared when data is written to I2CDXR.
1 I2CDXR ready: Data has been copied from I2CDXR to I2CXSR.
XRDY is also forced to 1 when the I2C module is reset.这说明, I2C 数据一直没有发出去,你最好检查一下总线波形,特别是 SCL 信号
