关于ADS1675中PLL的使用

TI的工程师你们好，我现在写ADS1675进行高速采集的程序，看时序图应该会使用PLL进行3倍频，但是这个PLL需要配置吗？一直达不到我想要的结果。谢谢大哥们，帮帮小弟呀

user5791039：

求大哥大姐回复一下鸭

user151383853：

The high-speed modes (DRATE = 100, 101) are supported in high-speed LVDS interface mode only. The state of the LVDS pin and the SCLK_SEL are ignored. In these two modes, an on-chip PLL is used to multiply the input clock (CLK) by three, to be used for the serial interface. This high-speed clock enables all 23-bit output data to be shifted out at the high data rate. The DRDY pulse in this case is three serial clocks wide. The on-chip PLL can lock to input clocks ranging from 8MHz to 32MHz. To conserve power, the PLL is enabled only in the high-speed modes. After power up as well as after the CLK signal is issued, if the CLK frequency is changed, and when switching from low-speed mode to high-speed mode, the PLL needs at least tLPLLSTL to lock on and generate a proper LVDS serial shift clock. Switching among the high-speed modes does not require the user to wait for the PLL to lock. While the PLL is locking on, DOUT and SCLK are held low. After the PLL has locked on, the SCLK pin outputs a continuous clock that is three times the frequency of CLK.

设置高速模式就可以

user5791039：

回复 user151383853:

哥哥你好 我已经设置好高速模式啦，可是SCLK没倍频，反而降低了。你可以看看我的程序吗，可以有偿。马上毕业了，所以有点着急。

Amy Luo：

您好，
ADS1675的高速模式（drate=100，101）只在高速LVDS接口模式下受支持，ADS1675外接是高速LVDS接口吗

user5791039：

回复 Amy Luo:

ADS1675我外接的是FPGA的普通IO管脚，应该不是高速的LVDS接口，这样的话有解决方法吗哥？

user5791039：

回复 Amy Luo:

我编程用了IBUFGDS，将差分转换成单端信号了，然后差分管脚连接是普通IO管脚，哥哥 求一个解决办法呀

Amy Luo：

回复 user5791039:

ADS1675的高速模式只在高速LVDS接口下使用，您可以咨询一下FPGA的技术支持，FPGA 是否具有高速LVDS接口。

user5791039：

回复 Amy Luo:

您好 工程师，首先感谢给我解答。然后我看一下SPARTAN_6手册，发现是是具有LVDS接口的。

user5791039：

回复 Amy Luo:

您好，我已经看了SPANTAN-6管脚是具有高速LVDS接口的，但是还是倍频不上，江湖救急鸭，我现在真的很抓狂!