求助，ADS131A04读出的通道数据全部为0

各位好，在使用ADS131A04的时候遇到问题， M0-M2，分别为IOVDD,GND,GND，AVDD为5V，外部参考源5V，目前SPI通讯正常，复位能得到正确的响应0xFF04，采用外部晶振4.096Mhz，CLK1的CLK_DIV设置为1，CLK2的ICLK_DIV和OSR分别设置为5和1，即采样率为4.096Mhz/2/10/2048=100hz，通过返回状态确认设置都成功。外部输入接入了3.3V的电压，使能4个通道后，能得到DRDY输出的低电平信号，读取数据后，状态字节0x2200并无异常，但是后面的4个通道数据全为0。

现在不知道问题出在哪里，希望能得到帮助和指导，非常感谢！

Kailyn Chen：

您好， 寄存器ADC_ENA的bit ENA[3:0] 是否有配置为1111， 使得all channels power up。
这几位默认值为0000，即为all channels power down，所以看下这个寄存器是否配置，导致输出disable。

user4093479：

回复 Kailyn Chen:

您好，非常感谢回复。4个通道都已经power up，并且通过回复的状态字节确认了设置成功。另外，我在参考官方的TIDA-00810中关于ADS131A04初始化部分代码时发现与datasheet中的流程不符，这点很奇怪：

//Send Unlock Command while(!verifyCommand(ADS131A04_UNCLOCK_ACK)) { sendCommand(ADS131A04_UNCLOCK_COMMAND); }

//Send Wake-up Command while(!verifyCommand(ADS131A04_WAKEUP_ACK)) { sendCommand(ADS131A04_WAKEUP_COMMAND); }

//Set Iclk divider to 2 while(!verifyCommand(WRITE_REGISTER_ACK(CLK1, CLK_DIV_2) )) { sendCommand(WRITE_REGISTER_COMMAND(CLK1, CLK_DIV_2)); }

#if SAMPLES_PER_10_SECONDS == 40000 //Sent Modclk divider to 8 and OSR=256 while(!verifyCommand(WRITE_REGISTER_ACK(CLK2, ICLK_DIV_8 | OSR_256))) { sendCommand(WRITE_REGISTER_COMMAND(CLK2, ICLK_DIV_8 | OSR_256)); }#elif SAMPLES_PER_10_SECONDS == 53333 //Sent Modclk divider to 6 and OSR=256 while(!verifyCommand(WRITE_REGISTER_ACK(CLK2, ICLK_DIV_6 | OSR_256))) { sendCommand(WRITE_REGISTER_COMMAND(CLK2, ICLK_DIV_6 | OSR_256)); }#endif

//high resolution mode, NO negative charge pump, internal reference; BIT5 is set because the User Guide mentions to always write 1 when writing to this register. while(!verifyCommand(WRITE_REGISTER_ACK(A_SYS_CFG, HRM | INT_REFEN | BIT5))) { sendCommand(WRITE_REGISTER_COMMAND(A_SYS_CFG, HRM | INT_REFEN| BIT5)); }

//This is mainly to have everything have a fixed frame size from now on. while(!verifyCommand_6words(WRITE_REGISTER_ACK(D_SYS_CFG, HIZDLY_12ns | DNDLY_12ns | FIXED))) { sendCommand(WRITE_REGISTER_COMMAND(D_SYS_CFG, HIZDLY_12ns | DNDLY_12ns | FIXED)); }

//Enable All ADCs while(!verifyCommand_6words(WRITE_REGISTER_ACK(ADC_ENA, ADC_ENA_ENABLE_ALL_CHANNELS))) { sendCommand_6words(WRITE_REGISTER_COMMAND(ADC_ENA, ADC_ENA_ENABLE_ALL_CHANNELS)); }

//CRC is valid on all bits received and transmitted, 12 ns after assert DONE when LSB shifted out, CRC enabled //12 ns time that the device asserts Hi-Z on DOUT after the LSB of the data frame is shifted out. while(!verifyCommand_6words(WRITE_REGISTER_ACK(D_SYS_CFG, HIZDLY_12ns | DNDLY_12ns | CRC_MODE | CRC_EN | FIXED))) { sendCommand_6words(WRITE_REGISTER_COMMAND(D_SYS_CFG, HIZDLY_12ns | DNDLY_12ns | CRC_MODE | CRC_EN | FIXED )); }

并不是手册中建议的解锁->配置->power up->wake up->上锁。而我是按照手册中建议的流程进行初始化的。