28027 scia fifo 接收中断

无法触发 fifo接收中断不知为何，代码如下：

#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
#include "com_define.h"
#include "Timer.h"

// Prototype statements for functions found within this file.
void scia_loopback_init(void);
void scia_fifo_init(void);
void scia_fifo_init2(void);
void scia_xmit(unsigned char dat);
void error(void);
void Scia_Rx_Init(void);
interrupt void scia_rx_isr(void);
interrupt void scia_tx_isr(void);
interrupt void sciaRxFifoIsr(void);
interrupt void sciaTxFifoIsr(void);

void scia_xmit_sendchar(void);
void COM1Tx_CheckSum(void);
void COM1Rx_CheckSum(void);
void Scia_Dataprocess(void);

void sciaInit2(void);

unsigned int Scia_RxBUF[Scia_RxBL];
unsigned int Scia_TxBUF[Scia_TxBL];
unsigned char Scia_Send_Complete=0;
unsigned char Scia_Rece_Complete=0;

unsigned char Scia_Requestrpm=0;
unsigned int Scia_Actualrpm=0;
unsigned int Scia_Rx_Cnt=0;

interrupt void cpu_timer0_isr(void);
interrupt void cpu_timer1_isr(void);
interrupt void cpu_timer2_isr(void);

void CPUTimer_Userset(struct CPUTIMER_VARS *Timer, float Freq, float Period);

void main(void)
{

InitGpio();
UART_Simulation_GPIO_Init();

InitSysCtrl();

InitSciGpio();

DINT;

InitPieCtrl();

IER = 0x0000;
IFR = 0x0000;

InitPieVectTable();

EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.SCIRXINTA = &sciaRxFifoIsr;
PieVectTable.SCITXINTA = &sciaTxFifoIsr;
EDIS; // This is needed to disable write to EALLOW protected registers
//
InitCpuTimers(); // For this example, only initialize the Cpu Timers
EnableInterrupts();

scia_fifo_init(); // Initialize the SCI FIFO
scia_loopback_init(); // Initalize SCI for digital loop back
// Note: Autobaud lock is not required for this example

CPUTimer_Userset(&CpuTimer0,10,100);
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.TINT0 = &cpu_timer0_isr;
PieVectTable.TINT1 = &cpu_timer1_isr;
PieVectTable.TINT2 = &cpu_timer2_isr;
EDIS; // This is needed to disable write to EALLOW protected registers

PieCtrlRegs.PIEIER1.bit.INTx7=1;
// Enable interrupts required for this example
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
PieCtrlRegs.PIEIER9.bit.INTx1=1; // PIE Group 9, INT1
PieCtrlRegs.PIEIER9.bit.INTx2=1; // PIE Group 9, INT2
IER = 0x100; // Enable CPU INT
EINT;

// Enable CPU int1 which is connected to CPU-Timer 0, CPU int13
// which is connected to CPU-Timer 1, and CPU int 14, which is connected
// to CPU-Timer 2:
IER |= M_INT1;
IER |= M_INT13;
IER |= M_INT14;
// Enable global Interrupts and higher priority real-time debug events:
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM

// PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

CpuTimer0Regs.PRD.all = mSec1;
CpuTimer1Regs.PRD.all = mSec5;
CpuTimer2Regs.PRD.all = mSec1000;

Scia_Rx_Init();

for(;;)
{
// DELAY_US(100000L);
if(Scia_Txwait>=500)
{
Scia_Txwait=0;
scia_xmit_sendchar();
GPIO_UART1_SendChar();
}
}

}

// Test 1,SCIA DLB, 8-bit word, baud rate 0x000F, default, 1 STOP bit, no parity
void scia_loopback_init()
{
// Note: Clocks were turned on to the SCIA peripheral
// in the InitSysCtrl() function
int16 BAUDRATE=SCI_PRD;

SciaRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback
// No parity,8 char bits,
// async mode, idle-line protocol
SciaRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK,
// Disable RX ERR, SLEEP, TXWAKE
SciaRegs.SCICTL2.all =0x0003;

SciaRegs.SCIHBAUD =BAUDRATE>>8;
SciaRegs.SCILBAUD =BAUDRATE;
SciaRegs.SCICCR.bit.LOOPBKENA =1; // Enable loop back
SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset

}

// Transmit a character from the SCI'
void scia_xmit(unsigned char dat)
{
while (SciaRegs.SCIFFTX.bit.TXFFST != 0) {}

SciaRegs.SCITXBUF=dat;

}

void scia_xmit_sendchar(void)
{
int i;
int CheckSum=0;
for(i=0;i<Scia_TxBL;i++)
Scia_TxBUF[i]=0x0;

Scia_TxBUF[0]=Scia_TxHeader;
Scia_TxBUF[1]=Scia_Actualrpm%256;
Scia_TxBUF[2]=(Scia_Actualrpm-(Scia_Actualrpm%256))/256;
// Scia_TxBUF[3]=0x08;
// Scia_TxBUF[4]=0x10;
// Scia_TxBUF[5]=0x20;
// Scia_TxBUF[6]=0x40;
// Scia_TxBUF[7]=0x80;

for(i=0;i<Scia_TxBL-1;i++)
{
scia_xmit(Scia_TxBUF[i]);
CheckSum+=Scia_TxBUF[i];
}

Scia_TxBUF[Scia_TxBL-1]=CheckSum;
scia_xmit(Scia_TxBUF[Scia_TxBL-1]);
COM1Tx_CheckSum();

}

void COM1Tx_CheckSum(void)
{

}

// Initalize the SCI FIFO
void scia_fifo_init()
{

SciaRegs.SCIFFTX.all=0xC022;

SciaRegs.SCIFFRX.all=0x0022;
SciaRegs.SCIFFCT.all=0x0;
SciaRegs.SCIFFTX.bit.TXFIFOXRESET=1;
SciaRegs.SCIFFRX.bit.RXFIFORESET=1;

}

void Scia_Rx_Init()

{
int i;
for(i=0;i<Scia_Rx_Cnt;i++)
{
Scia_RxBUF[Scia_Rx_Cnt-1]=0;
}
}

interrupt void sciaRxFifoIsr(void)
{
Scia_Rx_Cnt++;
while((SciaRegs.SCIFFRX.bit.RXFFINT!=0)&&(SciaRegs.SCIFFRX.bit.RXFFST!=0))
{
Scia_RxBUF[Scia_Rx_Cnt-1]=SciaRegs.SCIRXBUF.all;
}

SciaRegs.SCIFFRX.bit.RXFFOVRCLR=1;
SciaRegs.SCIFFRX.bit.RXFFINTCLR=1;
PieCtrlRegs.PIEACK.all|=0x100;

if(Scia_Rx_Cnt>=Scia_RxBL)
{
COM1Rx_CheckSum();
}

}

interrupt void sciaTxFifoIsr(void)
{

}

void COM1Rx_CheckSum(void)
{
int i;
unsigned char checksum;
for(i=0;i<Scia_RxBL-1;i++)
{
checksum+=Scia_RxBUF[i];
}
if(checksum==Scia_RxBUF[Scia_RxBL-1])
{
Scia_Rece_Complete=1;
Scia_Dataprocess();
}
else
{
Scia_Rece_Complete=0;
}
Scia_Rx_Cnt=0;
}

void Scia_Dataprocess(void)
{
Scia_Requestrpm=Scia_RxBUF[6];
Scia_Actualrpm=Scia_Requestrpm*30;
}

interrupt void cpu_timer0_isr(void)
{
CpuTimer0.InterruptCount++;
Scia_Txwait++;
// Acknowledge this interrupt to receive more interrupts from group 1
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}

interrupt void cpu_timer1_isr(void)
{
GpioDataRegs.GPATOGGLE.bit.GPIO2=1;
}

interrupt void cpu_timer2_isr(void)
{
GpioDataRegs.GPATOGGLE.bit.GPIO3=1;

}

void CPUTimer_Userset(struct CPUTIMER_VARS *Timer, float Freq, float Period)
{
Uint32 temp;

EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.TINT0 = &cpu_timer0_isr;
PieVectTable.TINT1 = &cpu_timer1_isr;
PieVectTable.TINT2 = &cpu_timer2_isr;
EDIS; // This is needed to disable write to EALLOW protected registers

PieCtrlRegs.PIEIER1.bit.INTx7=1;

// Enable CPU int1 which is connected to CPU-Timer 0, CPU int13
// which is connected to CPU-Timer 1, and CPU int 14, which is connected
// to CPU-Timer 2:
IER |= M_INT1;
IER |= M_INT13;
IER |= M_INT14;
// Enable global Interrupts and higher priority real-time debug events:
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM

PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

// Initialize timer period:
Timer->CPUFreqInMHz = Freq;
Timer->PeriodInUSec = Period;
temp = (long) (Freq * Period);
Timer->RegsAddr->PRD.all = temp;

CpuTimer0Regs.PRD.all = mSec1;
CpuTimer1Regs.PRD.all = mSec5;
CpuTimer2Regs.PRD.all = mSec1000;

// Set pre-scale counter to divide by 1 (SYSCLKOUT):
Timer->RegsAddr->TPR.all = 0;
Timer->RegsAddr->TPRH.all = 0;

// Initialize timer control register:
Timer->RegsAddr->TCR.bit.TSS = 1; // 1 = Stop timer, 0 = Start/Restart Timer
Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer
Timer->RegsAddr->TCR.bit.SOFT = 0;
Timer->RegsAddr->TCR.bit.FREE = 0; // Timer Free Run Disabled
Timer->RegsAddr->TCR.bit.TIE = 1; // 0 = Disable/ 1 = Enable Timer Interrupt

// Reset interrupt counter:
Timer->InterruptCount = 0;

CpuTimer0Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0
CpuTimer1Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0
CpuTimer2Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0
}

Eric Ma：

看你的代码，没找到有什么问题，不过你还是可以从TI的例程去测一下，然后做一下对比。

无法触发 fifo接收中断不知为何，代码如下：

#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
#include "com_define.h"
#include "Timer.h"

// Prototype statements for functions found within this file.
void scia_loopback_init(void);
void scia_fifo_init(void);
void scia_fifo_init2(void);
void scia_xmit(unsigned char dat);
void error(void);
void Scia_Rx_Init(void);
interrupt void scia_rx_isr(void);
interrupt void scia_tx_isr(void);
interrupt void sciaRxFifoIsr(void);
interrupt void sciaTxFifoIsr(void);

void scia_xmit_sendchar(void);
void COM1Tx_CheckSum(void);
void COM1Rx_CheckSum(void);
void Scia_Dataprocess(void);

void sciaInit2(void);

unsigned int Scia_RxBUF[Scia_RxBL];
unsigned int Scia_TxBUF[Scia_TxBL];
unsigned char Scia_Send_Complete=0;
unsigned char Scia_Rece_Complete=0;

unsigned char Scia_Requestrpm=0;
unsigned int Scia_Actualrpm=0;
unsigned int Scia_Rx_Cnt=0;

interrupt void cpu_timer0_isr(void);
interrupt void cpu_timer1_isr(void);
interrupt void cpu_timer2_isr(void);

void CPUTimer_Userset(struct CPUTIMER_VARS *Timer, float Freq, float Period);

void main(void)
{

InitGpio();
UART_Simulation_GPIO_Init();

InitSysCtrl();

InitSciGpio();

DINT;

InitPieCtrl();

IER = 0x0000;
IFR = 0x0000;

InitPieVectTable();

EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.SCIRXINTA = &sciaRxFifoIsr;
PieVectTable.SCITXINTA = &sciaTxFifoIsr;
EDIS; // This is needed to disable write to EALLOW protected registers
//
InitCpuTimers(); // For this example, only initialize the Cpu Timers
EnableInterrupts();

scia_fifo_init(); // Initialize the SCI FIFO
scia_loopback_init(); // Initalize SCI for digital loop back
// Note: Autobaud lock is not required for this example

CPUTimer_Userset(&CpuTimer0,10,100);
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.TINT0 = &cpu_timer0_isr;
PieVectTable.TINT1 = &cpu_timer1_isr;
PieVectTable.TINT2 = &cpu_timer2_isr;
EDIS; // This is needed to disable write to EALLOW protected registers

PieCtrlRegs.PIEIER1.bit.INTx7=1;
// Enable interrupts required for this example
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
PieCtrlRegs.PIEIER9.bit.INTx1=1; // PIE Group 9, INT1
PieCtrlRegs.PIEIER9.bit.INTx2=1; // PIE Group 9, INT2
IER = 0x100; // Enable CPU INT
EINT;

// Enable CPU int1 which is connected to CPU-Timer 0, CPU int13
// which is connected to CPU-Timer 1, and CPU int 14, which is connected
// to CPU-Timer 2:
IER |= M_INT1;
IER |= M_INT13;
IER |= M_INT14;
// Enable global Interrupts and higher priority real-time debug events:
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM

// PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

CpuTimer0Regs.PRD.all = mSec1;
CpuTimer1Regs.PRD.all = mSec5;
CpuTimer2Regs.PRD.all = mSec1000;

Scia_Rx_Init();

for(;;)
{
// DELAY_US(100000L);
if(Scia_Txwait>=500)
{
Scia_Txwait=0;
scia_xmit_sendchar();
GPIO_UART1_SendChar();
}
}

}

// Test 1,SCIA DLB, 8-bit word, baud rate 0x000F, default, 1 STOP bit, no parity
void scia_loopback_init()
{
// Note: Clocks were turned on to the SCIA peripheral
// in the InitSysCtrl() function
int16 BAUDRATE=SCI_PRD;

SciaRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback
// No parity,8 char bits,
// async mode, idle-line protocol
SciaRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK,
// Disable RX ERR, SLEEP, TXWAKE
SciaRegs.SCICTL2.all =0x0003;

SciaRegs.SCIHBAUD =BAUDRATE>>8;
SciaRegs.SCILBAUD =BAUDRATE;
SciaRegs.SCICCR.bit.LOOPBKENA =1; // Enable loop back
SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset

}

// Transmit a character from the SCI'
void scia_xmit(unsigned char dat)
{
while (SciaRegs.SCIFFTX.bit.TXFFST != 0) {}

SciaRegs.SCITXBUF=dat;

}

void scia_xmit_sendchar(void)
{
int i;
int CheckSum=0;
for(i=0;i<Scia_TxBL;i++)
Scia_TxBUF[i]=0x0;

Scia_TxBUF[0]=Scia_TxHeader;
Scia_TxBUF[1]=Scia_Actualrpm%256;
Scia_TxBUF[2]=(Scia_Actualrpm-(Scia_Actualrpm%256))/256;
// Scia_TxBUF[3]=0x08;
// Scia_TxBUF[4]=0x10;
// Scia_TxBUF[5]=0x20;
// Scia_TxBUF[6]=0x40;
// Scia_TxBUF[7]=0x80;

for(i=0;i<Scia_TxBL-1;i++)
{
scia_xmit(Scia_TxBUF[i]);
CheckSum+=Scia_TxBUF[i];
}

Scia_TxBUF[Scia_TxBL-1]=CheckSum;
scia_xmit(Scia_TxBUF[Scia_TxBL-1]);
COM1Tx_CheckSum();

}

void COM1Tx_CheckSum(void)
{

}

// Initalize the SCI FIFO
void scia_fifo_init()
{

SciaRegs.SCIFFTX.all=0xC022;

SciaRegs.SCIFFRX.all=0x0022;
SciaRegs.SCIFFCT.all=0x0;
SciaRegs.SCIFFTX.bit.TXFIFOXRESET=1;
SciaRegs.SCIFFRX.bit.RXFIFORESET=1;

}

void Scia_Rx_Init()

{
int i;
for(i=0;i<Scia_Rx_Cnt;i++)
{
Scia_RxBUF[Scia_Rx_Cnt-1]=0;
}
}

interrupt void sciaRxFifoIsr(void)
{
Scia_Rx_Cnt++;
while((SciaRegs.SCIFFRX.bit.RXFFINT!=0)&&(SciaRegs.SCIFFRX.bit.RXFFST!=0))
{
Scia_RxBUF[Scia_Rx_Cnt-1]=SciaRegs.SCIRXBUF.all;
}

SciaRegs.SCIFFRX.bit.RXFFOVRCLR=1;
SciaRegs.SCIFFRX.bit.RXFFINTCLR=1;
PieCtrlRegs.PIEACK.all|=0x100;

if(Scia_Rx_Cnt>=Scia_RxBL)
{
COM1Rx_CheckSum();
}

}

interrupt void sciaTxFifoIsr(void)
{

}

void COM1Rx_CheckSum(void)
{
int i;
unsigned char checksum;
for(i=0;i<Scia_RxBL-1;i++)
{
checksum+=Scia_RxBUF[i];
}
if(checksum==Scia_RxBUF[Scia_RxBL-1])
{
Scia_Rece_Complete=1;
Scia_Dataprocess();
}
else
{
Scia_Rece_Complete=0;
}
Scia_Rx_Cnt=0;
}

void Scia_Dataprocess(void)
{
Scia_Requestrpm=Scia_RxBUF[6];
Scia_Actualrpm=Scia_Requestrpm*30;
}

interrupt void cpu_timer0_isr(void)
{
CpuTimer0.InterruptCount++;
Scia_Txwait++;
// Acknowledge this interrupt to receive more interrupts from group 1
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}

interrupt void cpu_timer1_isr(void)
{
GpioDataRegs.GPATOGGLE.bit.GPIO2=1;
}

interrupt void cpu_timer2_isr(void)
{
GpioDataRegs.GPATOGGLE.bit.GPIO3=1;

}

void CPUTimer_Userset(struct CPUTIMER_VARS *Timer, float Freq, float Period)
{
Uint32 temp;

EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.TINT0 = &cpu_timer0_isr;
PieVectTable.TINT1 = &cpu_timer1_isr;
PieVectTable.TINT2 = &cpu_timer2_isr;
EDIS; // This is needed to disable write to EALLOW protected registers

PieCtrlRegs.PIEIER1.bit.INTx7=1;

// Enable CPU int1 which is connected to CPU-Timer 0, CPU int13
// which is connected to CPU-Timer 1, and CPU int 14, which is connected
// to CPU-Timer 2:
IER |= M_INT1;
IER |= M_INT13;
IER |= M_INT14;
// Enable global Interrupts and higher priority real-time debug events:
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM

PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

// Initialize timer period:
Timer->CPUFreqInMHz = Freq;
Timer->PeriodInUSec = Period;
temp = (long) (Freq * Period);
Timer->RegsAddr->PRD.all = temp;

CpuTimer0Regs.PRD.all = mSec1;
CpuTimer1Regs.PRD.all = mSec5;
CpuTimer2Regs.PRD.all = mSec1000;

// Set pre-scale counter to divide by 1 (SYSCLKOUT):
Timer->RegsAddr->TPR.all = 0;
Timer->RegsAddr->TPRH.all = 0;

// Initialize timer control register:
Timer->RegsAddr->TCR.bit.TSS = 1; // 1 = Stop timer, 0 = Start/Restart Timer
Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer
Timer->RegsAddr->TCR.bit.SOFT = 0;
Timer->RegsAddr->TCR.bit.FREE = 0; // Timer Free Run Disabled
Timer->RegsAddr->TCR.bit.TIE = 1; // 0 = Disable/ 1 = Enable Timer Interrupt

// Reset interrupt counter:
Timer->InterruptCount = 0;

CpuTimer0Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0
CpuTimer1Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0
CpuTimer2Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0
}

mangui zhang：

配置有些乱    没看出头绪    

应该是几处中断的配置   相互修改导致不合理

无法触发 fifo接收中断不知为何，代码如下：

#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
#include "com_define.h"
#include "Timer.h"

// Prototype statements for functions found within this file.
void scia_loopback_init(void);
void scia_fifo_init(void);
void scia_fifo_init2(void);
void scia_xmit(unsigned char dat);
void error(void);
void Scia_Rx_Init(void);
interrupt void scia_rx_isr(void);
interrupt void scia_tx_isr(void);
interrupt void sciaRxFifoIsr(void);
interrupt void sciaTxFifoIsr(void);

void scia_xmit_sendchar(void);
void COM1Tx_CheckSum(void);
void COM1Rx_CheckSum(void);
void Scia_Dataprocess(void);

void sciaInit2(void);

unsigned int Scia_RxBUF[Scia_RxBL];
unsigned int Scia_TxBUF[Scia_TxBL];
unsigned char Scia_Send_Complete=0;
unsigned char Scia_Rece_Complete=0;

unsigned char Scia_Requestrpm=0;
unsigned int Scia_Actualrpm=0;
unsigned int Scia_Rx_Cnt=0;

interrupt void cpu_timer0_isr(void);
interrupt void cpu_timer1_isr(void);
interrupt void cpu_timer2_isr(void);

void CPUTimer_Userset(struct CPUTIMER_VARS *Timer, float Freq, float Period);

void main(void)
{

InitGpio();
UART_Simulation_GPIO_Init();

InitSysCtrl();

InitSciGpio();

DINT;

InitPieCtrl();

IER = 0x0000;
IFR = 0x0000;

InitPieVectTable();

EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.SCIRXINTA = &sciaRxFifoIsr;
PieVectTable.SCITXINTA = &sciaTxFifoIsr;
EDIS; // This is needed to disable write to EALLOW protected registers
//
InitCpuTimers(); // For this example, only initialize the Cpu Timers
EnableInterrupts();

scia_fifo_init(); // Initialize the SCI FIFO
scia_loopback_init(); // Initalize SCI for digital loop back
// Note: Autobaud lock is not required for this example

CPUTimer_Userset(&CpuTimer0,10,100);
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.TINT0 = &cpu_timer0_isr;
PieVectTable.TINT1 = &cpu_timer1_isr;
PieVectTable.TINT2 = &cpu_timer2_isr;
EDIS; // This is needed to disable write to EALLOW protected registers

PieCtrlRegs.PIEIER1.bit.INTx7=1;
// Enable interrupts required for this example
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
PieCtrlRegs.PIEIER9.bit.INTx1=1; // PIE Group 9, INT1
PieCtrlRegs.PIEIER9.bit.INTx2=1; // PIE Group 9, INT2
IER = 0x100; // Enable CPU INT
EINT;

// Enable CPU int1 which is connected to CPU-Timer 0, CPU int13
// which is connected to CPU-Timer 1, and CPU int 14, which is connected
// to CPU-Timer 2:
IER |= M_INT1;
IER |= M_INT13;
IER |= M_INT14;
// Enable global Interrupts and higher priority real-time debug events:
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM

// PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

CpuTimer0Regs.PRD.all = mSec1;
CpuTimer1Regs.PRD.all = mSec5;
CpuTimer2Regs.PRD.all = mSec1000;

Scia_Rx_Init();

for(;;)
{
// DELAY_US(100000L);
if(Scia_Txwait>=500)
{
Scia_Txwait=0;
scia_xmit_sendchar();
GPIO_UART1_SendChar();
}
}

}

// Test 1,SCIA DLB, 8-bit word, baud rate 0x000F, default, 1 STOP bit, no parity
void scia_loopback_init()
{
// Note: Clocks were turned on to the SCIA peripheral
// in the InitSysCtrl() function
int16 BAUDRATE=SCI_PRD;

SciaRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback
// No parity,8 char bits,
// async mode, idle-line protocol
SciaRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK,
// Disable RX ERR, SLEEP, TXWAKE
SciaRegs.SCICTL2.all =0x0003;

SciaRegs.SCIHBAUD =BAUDRATE>>8;
SciaRegs.SCILBAUD =BAUDRATE;
SciaRegs.SCICCR.bit.LOOPBKENA =1; // Enable loop back
SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset

}

// Transmit a character from the SCI'
void scia_xmit(unsigned char dat)
{
while (SciaRegs.SCIFFTX.bit.TXFFST != 0) {}

SciaRegs.SCITXBUF=dat;

}

void scia_xmit_sendchar(void)
{
int i;
int CheckSum=0;
for(i=0;i<Scia_TxBL;i++)
Scia_TxBUF[i]=0x0;

Scia_TxBUF[0]=Scia_TxHeader;
Scia_TxBUF[1]=Scia_Actualrpm%256;
Scia_TxBUF[2]=(Scia_Actualrpm-(Scia_Actualrpm%256))/256;
// Scia_TxBUF[3]=0x08;
// Scia_TxBUF[4]=0x10;
// Scia_TxBUF[5]=0x20;
// Scia_TxBUF[6]=0x40;
// Scia_TxBUF[7]=0x80;

for(i=0;i<Scia_TxBL-1;i++)
{
scia_xmit(Scia_TxBUF[i]);
CheckSum+=Scia_TxBUF[i];
}

Scia_TxBUF[Scia_TxBL-1]=CheckSum;
scia_xmit(Scia_TxBUF[Scia_TxBL-1]);
COM1Tx_CheckSum();

}

void COM1Tx_CheckSum(void)
{

}

// Initalize the SCI FIFO
void scia_fifo_init()
{

SciaRegs.SCIFFTX.all=0xC022;

SciaRegs.SCIFFRX.all=0x0022;
SciaRegs.SCIFFCT.all=0x0;
SciaRegs.SCIFFTX.bit.TXFIFOXRESET=1;
SciaRegs.SCIFFRX.bit.RXFIFORESET=1;

}

void Scia_Rx_Init()

{
int i;
for(i=0;i<Scia_Rx_Cnt;i++)
{
Scia_RxBUF[Scia_Rx_Cnt-1]=0;
}
}

interrupt void sciaRxFifoIsr(void)
{
Scia_Rx_Cnt++;
while((SciaRegs.SCIFFRX.bit.RXFFINT!=0)&&(SciaRegs.SCIFFRX.bit.RXFFST!=0))
{
Scia_RxBUF[Scia_Rx_Cnt-1]=SciaRegs.SCIRXBUF.all;
}

SciaRegs.SCIFFRX.bit.RXFFOVRCLR=1;
SciaRegs.SCIFFRX.bit.RXFFINTCLR=1;
PieCtrlRegs.PIEACK.all|=0x100;

if(Scia_Rx_Cnt>=Scia_RxBL)
{
COM1Rx_CheckSum();
}

}

interrupt void sciaTxFifoIsr(void)
{

}

void COM1Rx_CheckSum(void)
{
int i;
unsigned char checksum;
for(i=0;i<Scia_RxBL-1;i++)
{
checksum+=Scia_RxBUF[i];
}
if(checksum==Scia_RxBUF[Scia_RxBL-1])
{
Scia_Rece_Complete=1;
Scia_Dataprocess();
}
else
{
Scia_Rece_Complete=0;
}
Scia_Rx_Cnt=0;
}

void Scia_Dataprocess(void)
{
Scia_Requestrpm=Scia_RxBUF[6];
Scia_Actualrpm=Scia_Requestrpm*30;
}

interrupt void cpu_timer0_isr(void)
{
CpuTimer0.InterruptCount++;
Scia_Txwait++;
// Acknowledge this interrupt to receive more interrupts from group 1
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}

interrupt void cpu_timer1_isr(void)
{
GpioDataRegs.GPATOGGLE.bit.GPIO2=1;
}

interrupt void cpu_timer2_isr(void)
{
GpioDataRegs.GPATOGGLE.bit.GPIO3=1;

}

void CPUTimer_Userset(struct CPUTIMER_VARS *Timer, float Freq, float Period)
{
Uint32 temp;

EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.TINT0 = &cpu_timer0_isr;
PieVectTable.TINT1 = &cpu_timer1_isr;
PieVectTable.TINT2 = &cpu_timer2_isr;
EDIS; // This is needed to disable write to EALLOW protected registers

PieCtrlRegs.PIEIER1.bit.INTx7=1;

// Enable CPU int1 which is connected to CPU-Timer 0, CPU int13
// which is connected to CPU-Timer 1, and CPU int 14, which is connected
// to CPU-Timer 2:
IER |= M_INT1;
IER |= M_INT13;
IER |= M_INT14;
// Enable global Interrupts and higher priority real-time debug events:
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM

PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

// Initialize timer period:
Timer->CPUFreqInMHz = Freq;
Timer->PeriodInUSec = Period;
temp = (long) (Freq * Period);
Timer->RegsAddr->PRD.all = temp;

CpuTimer0Regs.PRD.all = mSec1;
CpuTimer1Regs.PRD.all = mSec5;
CpuTimer2Regs.PRD.all = mSec1000;

// Set pre-scale counter to divide by 1 (SYSCLKOUT):
Timer->RegsAddr->TPR.all = 0;
Timer->RegsAddr->TPRH.all = 0;

// Initialize timer control register:
Timer->RegsAddr->TCR.bit.TSS = 1; // 1 = Stop timer, 0 = Start/Restart Timer
Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer
Timer->RegsAddr->TCR.bit.SOFT = 0;
Timer->RegsAddr->TCR.bit.FREE = 0; // Timer Free Run Disabled
Timer->RegsAddr->TCR.bit.TIE = 1; // 0 = Disable/ 1 = Enable Timer Interrupt

// Reset interrupt counter:
Timer->InterruptCount = 0;

CpuTimer0Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0
CpuTimer1Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0
CpuTimer2Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0
}

feng mao：

在SciaRegs.SCICTL1.all =0x0023; 之后加上下面两条语句。

SciaRegs.SCIFFTX.bit.TXFIFOXRESET=1;

SciaRegs.SCIFFRX.bit.RXFIFORESET=1;

在使用SW REST之后要把TXFIFOXRESET和RXFIFORESET也置位1，不然既不会接收也不会发送。