28069 ePWM模块间相移问题-TI中文支持网

在使用不同EPWM模块间移相设置时，EPwm4设置为up_down模式EPwm4Regs.TBPHS.half.TBPHS = (AlgorithmReg.PwmReg.LLC_PwmPeriod_Pre >> 1) ;// Phase is 90°，理论上可以得到90°的移相，在实际波形测试时相移位107°左右，需要-20才能得到90度相移，可以帮忙找下原因吗？谢谢！

配置代码如下：

/*************************************************************************/

#define BUCK_PWM_PERIOD (562) //Set PWM period =(90Mhz/80KHz)/2

#define LLC_PWM_PERIOD_80KHZ (562) //Set PWM period =(90Mhz/80KHz)/2

#define LLC_PWM_PERIOD_200KHZ (225) //Set PWM period =(90Mhz/200KHz)/2

void InitEPwm1(void)

{

/************************************************

* 1.0 Setup Time-Base(TB)

************************************************/

// Setup TBCLK

EPwm1Regs.TBPRD = BUCK_PWM_PERIOD; // Set timer period period

EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0

EPwm1Regs.TBCTR = 0x0000; // Clear counter

// Set Compare values

EPwm1Regs.CMPA.half.CMPA = BUCK_PWM_PERIOD;// Set compare A value

EPwm1Regs.CMPB = 0; // Set compare B value

// Setup counter mode

EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down

EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading

EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; // SYNC_DISABLE

EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT

EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; // TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV) = SYSCLKOUT

/************************************************

* 2.0 Setup Counter Compare(CC)

************************************************/

// Setup shadowing (CC)

EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Shadow mode.

EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero

EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

/************************************************

* 3.0 Setup Action Qualifier(AQ)

************************************************/

// Set actions （AQ）

EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count

EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on event A, down count

EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR ; // Clear PWM1B on event B, up count

EPwm1Regs.AQCTLB.bit.CBD = AQ_SET; // Set PWM1B on event B, down count

/************************************************

* 4.0 Setup Dead Band(DB)

************************************************/

EPwm1Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED; // EPWMxA In (from the action-qualifier) is the source for rising-edge delayed signal.

// EPWMxB In (from the action-qualifier) is the source for falling-edge delayed signal.

EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HI; // Active high (AH) mode. Neither EPWMxA nor EPWMxB is inverted (default).

EPwm1Regs.DBCTL.bit.OUT_MODE = DB_DISABLE; // Dead-band generation is bypassed for both output signals.

EPwm1Regs.DBRED = 45; // 500ns,not active

EPwm1Regs.DBFED = 45; // 500ns,not active

/************************************************

* 5.0 Setup PWM-Chopper (PC)

************************************************/

EPwm1Regs.PCCTL.bit.CHPEN = 0; // Disable (bypass) PWM chopping function

/************************************************

* 6.0 Digital Compare (DC)

************************************************/

/* 比较器过流保护关驱动操作 */

/* TZDCSEL\DCTRIPSEL\DCACTL\DCBCTL\DCFCTL\DCCAPCTL寄存器受保护 */

/* 必须开启. */

EALLOW;

// Define an event (DCAEVT1) as OSHT to lock PWM

EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_COMP1OUT; /* DCAH = Comparator 1 output */

EPwm1Regs.TZDCSEL.bit.DCAEVT1 = TZ_DCAH_HI; /* DCAEVT1 = DCAH low(will become active as Comparator output goes high)*/

EPwm1Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT1; /* DCAEVT1 = DCAEVT1 (not filtered) */

EPwm1Regs.DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC; /* Take async path */

EPwm1Regs.DCTRIPSEL.bit.DCBHCOMPSEL = DC_COMP1OUT;

EPwm1Regs.TZDCSEL.bit.DCBEVT1 = TZ_DCBH_HI;

EPwm1Regs.DCBCTL.bit.EVT1SRCSEL = DC_EVT1;

EPwm1Regs.DCBCTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC;

EDIS;

/************************************************

* 7.0 Trip Zone(TZ)

************************************************/

/* TZSEL/TZCTL/TZEINT/TZCLR/TZFRC/HRCNFG are EALLOW-protected registers */

// Enable DCAEVT1 and DCBEVT1 are one shot trip sources

// Note: DCxEVT1 events can be defined as one-shot.

// DCxEVT2 events can be defined as cycle-by-cycle.

EALLOW;

EPwm1Regs.TZSEL.bit.DCAEVT1 = 1; /* Enable DCAEVT1 as one-shot-trip source for this ePWM module.*/

EPwm1Regs.TZSEL.bit.DCBEVT1 = 1; /* Enable DCBEVT1 as one-shot-trip source for this ePWM module.*/

// DCAEVTx events can force EPWMxA

// DCBEVTx events can force EPWMxB

EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // 本项目使用软件出发TZ,EPWM1A will go low

EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // 本项目使用软件出发TZ,EPWM1B will go low

EPwm1Regs.TZCTL.bit.DCAEVT1 = TZ_FORCE_LO;

EPwm1Regs.TZCTL.bit.DCBEVT1 = TZ_FORCE_LO;

EDIS;

/************************************************

* 8.0 Event Trigger and Interrupt(ET)

************************************************/

// SOC

EPwm1Regs.ETSEL.bit.SOCAEN = 1; // 使能EPWMxSOCA;

EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTR_PRD; // TBCTR=TBTRD,时触发SOCA;

EPwm1Regs.ETPS.bit.SOCAPRD = ET_1ST; // Generate the EPWMxSOCA pulse on the first event

EPwm1Regs.ETSEL.bit.SOCBEN = 1; // 使能EPWMxSOCB;

EPwm1Regs.ETSEL.bit.SOCBSEL = ET_CTR_PRD; // TBCTR=TBTRD,时触发SOCB;

EPwm1Regs.ETPS.bit.SOCBPRD = ET_1ST; // Generate the EPWMxSOCB pulse on the first event

// Interrupt

EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event

EPwm1Regs.ETSEL.bit.INTEN = 1; // 使能Enable INT,外设级中断允许

EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate an interrupt on the first event

}

/**********************************************************************

* Function: InitEPwm2()

* Description: Initializes the EPwm2 module on the F2806x.

* 将PWM2A与PWM2B配置成互补驱动，以PWM1A为信号源

* 上升沿死区：500ns

* 下降沿死区：500ns

**********************************************************************/

void InitEPwm2(void)

{

/************************************************

* 1.0 Setup Time-Base(TB)

************************************************/

// Setup TBCLK

EPwm2Regs.TBPRD = LLC_PWM_PERIOD_200KHZ; // Set timer period period

EPwm2Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0

EPwm2Regs.TBCTR = 0x0000; // Clear counter

// Set Compare values

EPwm2Regs.CMPA.half.CMPA = LLC_PWM_PERIOD_200KHZ;// Set compare A value

EPwm2Regs.CMPB = 0; // Set compare B value

// Setup counter mode

EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down

EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading

EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // CTR = zero时输出同步信号，EPWM2同步用

EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT

EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; // TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV) = SYSCLKOUT

/************************************************

* 2.0 Setup Counter Compare(CC)

************************************************/

// Setup shadowing (CC)

EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Shadow mode.

EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero

EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

/************************************************

* 3.0 Setup Action Qualifier(AQ)

************************************************/

// Set actions （AQ）

EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count

EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on event A, down count

EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR ; // Clear PWM1B on event B, up count

EPwm2Regs.AQCTLB.bit.CBD = AQ_SET; // Set PWM1B on event B, down count

/************************************************

* 4.0 Setup Dead Band(DB)

************************************************/

EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL; // EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay.

EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active high (AH) mode. Neither EPWMxA nor EPWMxB is inverted (default).

EPwm2Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;//DB_FULL_ENABLE; // Dead-band generation is bypassed for both output signals.

EPwm2Regs.DBRED = 45; // Rising-edge delay 500ns is active.

EPwm2Regs.DBFED = 45; // Fising-edge delay 500ns is active.

/************************************************

* 5.0 Setup PWM-Chopper (PC)

************************************************/

EPwm2Regs.PCCTL.bit.CHPEN = 0; // Disable (bypass) PWM chopping function

/************************************************

* 6.0 Digital Compare (DC)

************************************************/

/************************************************

* 6.0 Digital Compare (DC)

************************************************/

/* 比较器过流保护关驱动操作 */

/* TZDCSEL\DCTRIPSEL\DCACTL\DCBCTL\DCFCTL\DCCAPCTL寄存器受保护 */

/* 必须开启. */

EALLOW;

// Define an event (DCAEVT1) as OSHT to lock PWM

EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_COMP1OUT; /* DCAH = Comparator 1 output */

EPwm2Regs.TZDCSEL.bit.DCAEVT1 = TZ_DCAH_HI; /* DCAEVT1 = DCAH low(will become active as Comparator output goes high)*/

EPwm2Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT1; /* DCAEVT1 = DCAEVT1 (not filtered) */

EPwm2Regs.DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC; /* Take async path */

EPwm2Regs.DCTRIPSEL.bit.DCBHCOMPSEL = DC_COMP1OUT;

EPwm2Regs.TZDCSEL.bit.DCBEVT1 = TZ_DCBH_HI;

EPwm2Regs.DCBCTL.bit.EVT1SRCSEL = DC_EVT1;

EPwm2Regs.DCBCTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC;

EDIS;

/************************************************

* 7.0 Trip Zone(TZ)

************************************************/

/* TZSEL/TZCTL/TZEINT/TZCLR/TZFRC/HRCNFG are EALLOW-protected registers */

// Enable DCAEVT1 and DCBEVT1 are one shot trip sources

// Note: DCxEVT1 events can be defined as one-shot.

// DCxEVT2 events can be defined as cycle-by-cycle.

EALLOW;

EPwm2Regs.TZSEL.bit.DCAEVT1 = 1; /* Enable DCAEVT1 as one-shot-trip source for this ePWM module.*/

EPwm2Regs.TZSEL.bit.DCBEVT1 = 1; /* Enable DCBEVT1 as one-shot-trip source for this ePWM module.*/

// DCAEVTx events can force EPWMxA

// DCBEVTx events can force EPWMxB

EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // 本项目使用软件出发TZ,EPWM1A will go low

EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // 本项目使用软件出发TZ,EPWM1B will go low

EPwm2Regs.TZCTL.bit.DCAEVT1 = TZ_FORCE_LO;

EPwm2Regs.TZCTL.bit.DCBEVT1 = TZ_FORCE_LO;

EDIS;

/************************************************

* 8.0 Event Trigger and Interrupt(ET)

************************************************/

// SOC

//None

// Interrupt

EPwm2Regs.ETSEL.bit.INTSEL = ET_DCAEVT1SOC; // Select INT on Zero event

EPwm2Regs.ETSEL.bit.INTEN = 0; // Disable INT, 外设级中断允许

EPwm2Regs.ETPS.bit.INTPRD = ET_DISABLE; // Generate an interrupt on the first event

}

/**********************************************************************

* Function: InitEPwm3()

* Description: Initializes the EPwm3 module on the F2806x.

* 将PWM2A与PWM2B配置成互补驱动，以PWM1A为信号源

* 上升沿死区：500ns

* 下降沿死区：500ns

**********************************************************************/

void InitEPwm3(void)

{

/************************************************

* 1.0 Setup Time-Base(TB)

************************************************/

// Setup TBCLK

EPwm3Regs.TBPRD = LLC_PWM_PERIOD_200KHZ; // Set timer period period

EPwm3Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0

EPwm3Regs.TBCTR = 0x0000; // Clear counter

// Set Compare values

EPwm3Regs.CMPA.half.CMPA = LLC_PWM_PERIOD_200KHZ; // Set compare A value

EPwm3Regs.CMPB = 0; // Set compare B value

// Setup counter mode

EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down

EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading

EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;//TB_CTR_ZERO; // CTR = zero时输出同步信号，EPWM2同步用

EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT

EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; // TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV) = SYSCLKOUT

/************************************************

* 2.0 Setup Counter Compare(CC)

************************************************/

// Setup shadowing (CC)

EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Shadow mode.

EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero

EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

/************************************************

* 3.0 Setup Action Qualifier(AQ)

************************************************/

// Set actions （AQ）

* 变压器需要取反,2015.12.01

EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count

EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on event A, down count

EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Clear PWM1B on event B, up count

EPwm3Regs.AQCTLB.bit.CBD = AQ_SET; // Set PWM1B on event B, down count

EPwm3Regs.AQCTLA.bit.CBU = AQ_CLEAR; // Set PWM1A on event A, up count

EPwm3Regs.AQCTLA.bit.CBD = AQ_SET; // Clear PWM1A on event A, down count

EPwm3Regs.AQCTLB.bit.CAU = AQ_SET; // Clear PWM1B on event B, up count

EPwm3Regs.AQCTLB.bit.CAD = AQ_CLEAR; // Set PWM1B on event B, down count

/************************************************

* 4.0 Setup Dead Band(DB)

************************************************/

EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL; // EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay.

EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active high (AH) mode. Neither EPWMxA nor EPWMxB is inverted (default).

EPwm3Regs.DBCTL.bit.OUT_MODE = DB_DISABLE; // Dead-band generation is bypassed for both output signals.

EPwm3Regs.DBRED = 45; // Rising-edge delay 500ns is active.

EPwm3Regs.DBFED = 45; // Fising-edge delay 500ns is active.

/************************************************

* 5.0 Setup PWM-Chopper (PC)

************************************************/

EPwm3Regs.PCCTL.bit.CHPEN = 0; // Disable (bypass) PWM chopping function

/************************************************

* 6.0 Digital Compare (DC)

************************************************/

/************************************************

* 6.0 Digital Compare (DC)

************************************************/

/* 比较器过流保护关驱动操作 */

/* TZDCSEL\DCTRIPSEL\DCACTL\DCBCTL\DCFCTL\DCCAPCTL寄存器受保护 */

/* 必须开启. */

EALLOW;

// Define an event (DCAEVT1) as OSHT to lock PWM

EPwm3Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_COMP1OUT; /* DCAH = Comparator 1 output */

EPwm3Regs.TZDCSEL.bit.DCAEVT1 = TZ_DCAH_HI; /* DCAEVT1 = DCAH low(will become active as Comparator output goes high)*/

EPwm3Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT1; /* DCAEVT1 = DCAEVT1 (not filtered) */

EPwm3Regs.DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC; /* Take async path */

EPwm3Regs.DCTRIPSEL.bit.DCBHCOMPSEL = DC_COMP1OUT;

EPwm3Regs.TZDCSEL.bit.DCBEVT1 = TZ_DCBH_HI;

EPwm3Regs.DCBCTL.bit.EVT1SRCSEL = DC_EVT1;

EPwm3Regs.DCBCTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC;

EDIS;

/************************************************

* 7.0 Trip Zone(TZ)

************************************************/

/* TZSEL/TZCTL/TZEINT/TZCLR/TZFRC/HRCNFG are EALLOW-protected registers */

// Enable DCAEVT1 and DCBEVT1 are one shot trip sources

// Note: DCxEVT1 events can be defined as one-shot.

// DCxEVT2 events can be defined as cycle-by-cycle.

EALLOW;

EPwm3Regs.TZSEL.bit.DCAEVT1 = 1; /* Enable DCAEVT1 as one-shot-trip source for this ePWM module.*/

EPwm3Regs.TZSEL.bit.DCBEVT1 = 1; /* Enable DCBEVT1 as one-shot-trip source for this ePWM module.*/

// DCAEVTx events can force EPWMxA

// DCBEVTx events can force EPWMxB

EPwm3Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // 本项目使用软件出发TZ,EPWM1A will go low

EPwm3Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // 本项目使用软件出发TZ,EPWM1B will go low

EPwm3Regs.TZCTL.bit.DCAEVT1 = TZ_FORCE_LO;

EPwm3Regs.TZCTL.bit.DCBEVT1 = TZ_FORCE_LO;

EDIS;

/************************************************

* 8.0 Event Trigger and Interrupt(ET)

************************************************/

// SOC

//None

// Interrupt

EPwm3Regs.ETSEL.bit.INTSEL = ET_DCAEVT1SOC; // Select INT on Zero event

EPwm3Regs.ETSEL.bit.INTEN = 0; // Disable INT, 外设级中断允许

EPwm3Regs.ETPS.bit.INTPRD = ET_DISABLE; // Generate an interrupt on the first event

}

/**********************************************************************

* Function: InitEPwm4()

* Description: Initializes the EPwm4 module on the F2806x.

* 与EPwm1，EPwm4移向90度,

* 将PWM4A与PWM4B配置成互补驱动，以PWM4A为信号源

* 上升沿死区：500ns

* 下降沿死区：500ns

**********************************************************************/

void InitEPwm4(void)

{

/************************************************

* 1.0 Setup Time-Base(TB)

************************************************/

// Setup TBCLK

EPwm4Regs.TBPRD = LLC_PWM_PERIOD_200KHZ; // Set timer period period

EPwm4Regs.TBPHS.half.TBPHS = (LLC_PWM_PERIOD_200KHZ >> 1);// Phase is 90°

EPwm4Regs.TBCTR = 0x0000; // Clear counter

// Set Compare values

EPwm4Regs.CMPA.half.CMPA = LLC_PWM_PERIOD_200KHZ; // Set compare A value

EPwm4Regs.CMPB = 0; // Set compare B value

// Setup counter mode

EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down

EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Phase loading

EPwm4Regs.TBCTL.bit.PHSDIR = TB_DOWN; // Count DOWN on sync (=90 deg)

EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW; // The period register (TBPRD) is loaded from its shadow register

// when the time-base counter,TBCTR, is equal to zero.

EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // CTR = zero时输出同步信号，EPWM2同步用

EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT

EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1; // TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV) = SYSCLKOUT

/************************************************

* 2.0 Setup Counter Compare(CC)

************************************************/

// Setup shadowing (CC)

EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Shadow mode.

EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero

EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

/************************************************

* 3.0 Setup Action Qualifier(AQ)

************************************************/

// Set actions （AQ）

EPwm4Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count

EPwm4Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on event A, down count

EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR ; // Clear PWM1B on event B, up count

EPwm4Regs.AQCTLB.bit.CBD = AQ_SET; // Set PWM1B on event B, down count

/************************************************

* 4.0 Setup Dead Band(DB)

************************************************/

EPwm4Regs.DBCTL.bit.IN_MODE = DBA_ALL; // EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay.

EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active high (AH) mode. Neither EPWMxA nor EPWMxB is inverted (default).

EPwm4Regs.DBCTL.bit.OUT_MODE = DB_DISABLE; // Dead-band generation is bypassed for both output signals.

EPwm4Regs.DBRED = 45; // 500ns,not active

EPwm4Regs.DBFED = 45; // 500ns,not active

/************************************************

* 5.0 Setup PWM-Chopper (PC)

************************************************/

EPwm4Regs.PCCTL.bit.CHPEN = 0; // Disable (bypass) PWM chopping function

/************************************************

* 6.0 Digital Compare (DC)

************************************************/

/************************************************

* 6.0 Digital Compare (DC)

************************************************/

/* 比较器过流保护关驱动操作 */

/* TZDCSEL\DCTRIPSEL\DCACTL\DCBCTL\DCFCTL\DCCAPCTL寄存器受保护 */

/* 必须开启. */

EALLOW;

// Define an event (DCAEVT1) as OSHT to lock PWM

EPwm4Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_COMP1OUT; /* DCAH = Comparator 1 output */

EPwm4Regs.TZDCSEL.bit.DCAEVT1 = TZ_DCAH_HI; /* DCAEVT1 = DCAH low(will become active as Comparator output goes high)*/

EPwm4Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT1; /* DCAEVT1 = DCAEVT1 (not filtered) */

EPwm4Regs.DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC; /* Take async path */

EPwm4Regs.DCTRIPSEL.bit.DCBHCOMPSEL = DC_COMP1OUT;

EPwm4Regs.TZDCSEL.bit.DCBEVT1 = TZ_DCBH_HI;

EPwm4Regs.DCBCTL.bit.EVT1SRCSEL = DC_EVT1;

EPwm4Regs.DCBCTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC;

EDIS;

/************************************************

* 7.0 Trip Zone(TZ)

************************************************/

/* TZSEL/TZCTL/TZEINT/TZCLR/TZFRC/HRCNFG are EALLOW-protected registers */

// Enable DCAEVT1 and DCBEVT1 are one shot trip sources

// Note: DCxEVT1 events can be defined as one-shot.

// DCxEVT2 events can be defined as cycle-by-cycle.

EALLOW;

EPwm4Regs.TZSEL.bit.DCAEVT1 = 1; /* Enable DCAEVT1 as one-shot-trip source for this ePWM module.*/

EPwm4Regs.TZSEL.bit.DCBEVT1 = 1; /* Enable DCBEVT1 as one-shot-trip source for this ePWM module.*/

// DCAEVTx events can force EPWMxA

// DCBEVTx events can force EPWMxB

EPwm4Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // 本项目使用软件出发TZ,EPWM1A will go low

EPwm4Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // 本项目使用软件出发TZ,EPWM1B will go low

EPwm4Regs.TZCTL.bit.DCAEVT1 = TZ_FORCE_LO;

EPwm4Regs.TZCTL.bit.DCBEVT1 = TZ_FORCE_LO;

EDIS;

/************************************************

* 8.0 Event Trigger and Interrupt(ET)

************************************************/

// SOC

EPwm4Regs.ETSEL.bit.SOCBEN = 1; // 使能EPWMxSOCB;

EPwm4Regs.ETSEL.bit.SOCBSEL = ET_CTR_PRD; // TBCTR=TBTRD,时触发SOCB;

EPwm4Regs.ETPS.bit.SOCBPRD = ET_1ST; // Generate the EPWMxSOCA pulse on the first event

// Interrupt

EPwm4Regs.ETSEL.bit.INTSEL = ET_DCAEVT1SOC; // Select INT on Zero event

EPwm4Regs.ETSEL.bit.INTEN = 0; // Disable INT, 外设级中断允许

EPwm4Regs.ETPS.bit.INTPRD = ET_DISABLE; // Generate an interrupt on the first event

}

/**********************************************************************

* Function: InitEPwm5()

* Description: Initializes the EPwm4 module on the F2806x.

* 与EPwm4，EPwm5同相，都与EPwm1移向90度,

* 将PWM5A与PWM5B配置成互补驱动，以PWM5A为信号源

* 上升沿死区：500ns

* 下降沿死区：500ns

**********************************************************************/

void InitEPwm5(void)

{

/************************************************

* 1.0 Setup Time-Base(TB)

************************************************/

// Setup TBCLK

EPwm5Regs.TBPRD = LLC_PWM_PERIOD_200KHZ; // Set timer period period

EPwm5Regs.TBPHS.half.TBPHS = (LLC_PWM_PERIOD_200KHZ >> 1);// Phase is 90

EPwm5Regs.TBCTR = 0x0000; // Clear counter

// Set Compare values

EPwm5Regs.CMPA.half.CMPA = LLC_PWM_PERIOD_200KHZ; // Set compare A value

EPwm5Regs.CMPB = 0; // Set compare B value

// Setup counter mode

EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down

EPwm5Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Enable phase loading

EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through

EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT

EPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV1; // TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV) = SYSCLKOUT

/************************************************

* 2.0 Setup Counter Compare(CC)

************************************************/

// Setup shadowing (CC)

EPwm5Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Shadow mode.

EPwm5Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

EPwm5Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero

EPwm5Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

/************************************************

* 3.0 Setup Action Qualifier(AQ)

************************************************/

// Set actions （AQ）

* 变压器需要取反,2015.12.01

EPwm5Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count

EPwm5Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on event A, down count

EPwm5Regs.AQCTLB.bit.CBU = AQ_CLEAR ; // Clear PWM1B on event B, up count

EPwm5Regs.AQCTLB.bit.CBD = AQ_SET; // Set PWM1B on event B, down count

EPwm5Regs.AQCTLA.bit.CBU = AQ_CLEAR; // Set PWM1A on event A, up count

EPwm5Regs.AQCTLA.bit.CBD = AQ_SET; // Clear PWM1A on event A, down count

EPwm5Regs.AQCTLB.bit.CAU = AQ_SET ; // Clear PWM1B on event B, up count

EPwm5Regs.AQCTLB.bit.CAD = AQ_CLEAR; // Set PWM1B on event B, down count

/************************************************

* 4.0 Setup Dead Band(DB)

************************************************/

EPwm5Regs.DBCTL.bit.IN_MODE = DBA_ALL; // EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay.

EPwm5Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active high (AH) mode. Neither EPWMxA nor EPWMxB is inverted (default).

EPwm5Regs.DBCTL.bit.OUT_MODE = DB_DISABLE; // Dead-band generation is bypassed for both output signals.

EPwm5Regs.DBRED = 45; // 500ns,not active

EPwm5Regs.DBFED = 45; // 500ns,not active

/************************************************

* 5.0 Setup PWM-Chopper (PC)

************************************************/

EPwm5Regs.PCCTL.bit.CHPEN = 0; // Disable (bypass) PWM chopping function

/************************************************

* 6.0 Digital Compare (DC)

************************************************/

/************************************************

* 6.0 Digital Compare (DC)

************************************************/

/* 比较器过流保护关驱动操作 */

/* TZDCSEL\DCTRIPSEL\DCACTL\DCBCTL\DCFCTL\DCCAPCTL寄存器受保护 */

/* 必须开启. */

EALLOW;

// Define an event (DCAEVT1) as OSHT to lock PWM

EPwm5Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_COMP1OUT; /* DCAH = Comparator 1 output */

EPwm5Regs.TZDCSEL.bit.DCAEVT1 = TZ_DCAH_HI; /* DCAEVT1 = DCAH low(will become active as Comparator output goes high)*/

EPwm5Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT1; /* DCAEVT1 = DCAEVT1 (not filtered) */

EPwm5Regs.DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC; /* Take async path */

EPwm5Regs.DCTRIPSEL.bit.DCBHCOMPSEL = DC_COMP1OUT;

EPwm5Regs.TZDCSEL.bit.DCBEVT1 = TZ_DCBH_HI;

EPwm5Regs.DCBCTL.bit.EVT1SRCSEL = DC_EVT1;

EPwm5Regs.DCBCTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC;

EDIS;

/************************************************

* 7.0 Trip Zone(TZ)

************************************************/

/* TZSEL/TZCTL/TZEINT/TZCLR/TZFRC/HRCNFG are EALLOW-protected registers */

// Enable DCAEVT1 and DCBEVT1 are one shot trip sources

// Note: DCxEVT1 events can be defined as one-shot.

// DCxEVT2 events can be defined as cycle-by-cycle.

EALLOW;

EPwm5Regs.TZSEL.bit.DCAEVT1 = 1; /* Enable DCAEVT1 as one-shot-trip source for this ePWM module.*/

EPwm5Regs.TZSEL.bit.DCBEVT1 = 1; /* Enable DCBEVT1 as one-shot-trip source for this ePWM module.*/

// DCAEVTx events can force EPWMxA

// DCBEVTx events can force EPWMxB

EPwm5Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // 本项目使用软件出发TZ,EPWM1A will go low

EPwm5Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // 本项目使用软件出发TZ,EPWM1B will go low

EPwm5Regs.TZCTL.bit.DCAEVT1 = TZ_FORCE_LO;

EPwm5Regs.TZCTL.bit.DCBEVT1 = TZ_FORCE_LO;

EDIS;

/************************************************

* 8.0 Event Trigger and Interrupt(ET)

************************************************/

// SOC

// EPwm5Regs.ETSEL.bit.SOCBEN = 1; // 使能EPWMxSOCB;

// EPwm5Regs.ETSEL.bit.SOCBSEL = ET_CTR_PRD; // TBCTR=TBTRD,时触发SOCB;

// EPwm5Regs.ETPS.bit.SOCBPRD = ET_1ST; // Generate the EPWMxSOCA pulse on the first event

// Interrupt

EPwm5Regs.ETSEL.bit.INTSEL = ET_DCAEVT1SOC; // Select INT on Zero event

EPwm5Regs.ETSEL.bit.INTEN = 0; // Disable INT, 外设级中断允许

EPwm5Regs.ETPS.bit.INTPRD = ET_DISABLE; // Generate an interrupt on the first event

}

mangui zhang：

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